Non-homogeneous multi-processor system with shared memory

• US 20060190614A1
• Filed: 02/24/2005
• Published: 08/24/2006
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Johns, Charles Ray, Wellman, John-David, Hofstee, Harm Peter, Sathaye, Sumedh W., Gschwind, Michael Karl, Altman, Erik Richter, Kahle, James Allan, Hopkins, Martin E., Capek, Peter George
• Granted Patent: US 7,509,457 B2
• Time in Patent Office: Days
• US Class Current: 709/230
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/4862 the task being a mobile agent, i.e. specifically designed to migrate
• CPC Class Codes: H04L 63/168 above the transport layer
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Claims

1. A system comprising:

one or more first microprocessor with a first cache memory and a first address translation mechanism consistent with a set of page table entries; and

one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries.

2. The system of claim 1 further comprising:

a bus interconnecting the first processors and the second processors, the bus supporting coherent direct memory access.

3. The system of claim 1 wherein the first processor includes a reduced instruction set computer architecture with memory access governed by page and segment tables, and the set of page table entries is consistent with the reduced instruction set computer architecture.

4. The system of claim 1 wherein the second processors are single instruction multiple data processors with a unified register file and sequential instruction set semantics.

5. The system of claim 1 wherein the system is implemented on a single silicon die substrate.

6. The system of claim 1 wherein each of the second processors includes a local memory that is not a cache type memory.

7. The system of claim 1 wherein each of the second processors includes a local memory that is not cached.

8. The system of claim 7 wherein the one or more of the direct memory access controllers support direct memory access transactions between a plurality of the local memories included in the second processors.

9. The system of claim 1 wherein the second processors do not perform address translation for accessing a local memory with load and store instructions.

10. The system of claim 1 wherein the second processors access a system memory by issuing direct memory access commands that specify virtual memory addresses.

11. The system of claim 10 wherein the direct memory access controller translates between the virtual memory addresses and real memory addresses.

12. The system of claim 1 wherein an operating system executes on one of the first processors.

13. The system of claim 1 wherein a software program that is executed on the first processor schedules tasks to be performed on the second processors.

14. The system of claim 13 wherein the tasks are structured as remote procedure calls.

15. The system of claim 1 wherein the system is implemented on multiple silicon die.

16. The system of claim 15 wherein the multiple silicon die include an on-chip coherent bus and an off-chip coherent bus.

17. The system of claim 1 wherein the second processors are structured to support real-time tasks.

18. The system of claim 1 wherein the direct memory access controller is a synchronization point between the first processors and the second processors.

19. The system of claim 1 wherein the direct memory access controller transmits commands between the first processors and the second processors, wherein at least one of the commands is selected from the group consisting of copying data to a local storage area included in the second processors, initiating execution on the second processors at a specific address location, copying data from the local storage are included in the second processors to a main memory location, transmitting a notification event from the second processor to the first processor, and suspending execution of one of the second processors.

20. The system of claim 1 wherein the direct memory access controller is the only means of communication between the first processors and the second processors.

21. The system of claim 1 wherein the first processor is based upon a Power Architecture.

22. A system comprising:

one or more first microprocessors with a first cache memory and a first address translation mechanism consistent with a set of page table entries, wherein each of the first processors include a reduced instruction set computer architecture with memory access governed by page and segment tables, and the set of page table entries is consistent with the reduced instruction set computer architecture;

one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries, wherein the second processors are single instruction multiple data processors with a unified register file and sequential instruction set semantics; and

a bus interconnecting the first processors and the second processors, the bus supporting coherent direct memory access.

23. A system comprising:

one or more first microprocessor with a first cache memory and a first address translation mechanism consistent with a set of page table entries, wherein an operating system executes on one of the first processors; and

one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries, wherein the second processors access a system memory by issuing direct memory access commands that specify virtual memory addresses, the direct memory access controller adapted to translate between the virtual memory addresses and real memory addresses.