Computer chip set having on board wireless on board wireless interfaces to support parallel communication

• US 20060190634A1
• Filed: 06/15/2005
• Published: 08/24/2006
• Est. Priority Date: 02/07/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bennett, James D., Karaoguz, Jeyhan
• Granted Patent: US 7,975,079 B2
• Time in Patent Office: Days
• US Class Current: 710/15
• CPC Class Codes: H04M 1/0256 wherein the modules are operable in the detached state, e.g. one module for the user interface and one module for the transceiver
• CPC Class Codes: H04M 1/6058 involving the use of a headset accessory device connected to the portable telephone
• CPC Class Codes: H04M 1/72412 using two-way short-range wireless interfaces
• CPC Class Codes: H04W 84/02 Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]

Abstract

A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Claims

1. A computer system, comprising:

a processor motherboard including a processor for controlling operations and prompting communications within the computer system;

a memory controller device coupled to the processor motherboard for controlling access to memory and operable to communicate on a PCI bus within the computer system;

an input and output controller device for controlling input and output communications with off-board devices, the input and output controller device operable to communicate on the PCI bus with the memory controller device wherein the PCI bus provides a primary communication link between the memory controller device and the input and output controller device; and

a plurality of wireless interface devices forming a wireless communication link in at least two of the processor motherboard, the memory controller device and the input and output controller device wherein the alternate wireless communication link is operable as an alternate link to a primary wired communication link.

2. The computer system of claim 1 wherein each of the processor motherboard, the memory controller device and the input and output controller device having a wireless interface link further includes logic for controlling and monitoring communications over a corresponding primary wired communication link and further wherein the wireless interface link serves as an alternate communication link to the primary wired communication link.

3. The computer system of claim 1 further including at least one external device operably coupled to communicate with at least one of the processor motherboard, the memory controller device and the input and output controller device by way of the alternate wireless communication link.

4. The computer system of claim 3 wherein the wireless communication link is an alternate link to a secondary device and further wherein a primary external device is operably coupled to communicate with at least one of the processor motherboard, the memory controller device and the input and output controller device by way of the primary wired communication link.

5. The computer system of claim 3 wherein the alternate wireless communication link is an alternate communication link to a wired communication link to the at least one external device.

6. The computer system of claim 1 wherein the memory controller device is a Northbridge chip and wherein the input and output controller device is a Southbridge chip.

7. The computer system of claim 1 wherein the memory controller device is a memory controller hub of a hub architecture and wherein the input and output controller device is an input/output (I/O) controller hub of the hub architecture.

8. The computer system of claim 1 further comprising wireless interfaces forming an alternate communication link in each of the processor motherboard, the memory controller device and the input and output controller device.

9. A method to integrate computer system components, comprising:

creating an alternate wireless connection between embedded wireless interfaces within a plurality of integrated circuits; and

operably coupling at least two of the integrated circuits with a wireless communication pathway and a wired communication pathway.

10. The method of claim 9, wherein a first integrated circuit comprises a processor and a second integrated circuit comprises a chipset for controlled memory and I/O operations.

11. The method of claim 9, wherein the first integrated circuit comprises a baseboard management controller and the second integrated circuit comprises a remote device.

12. The method of claim 9 further including monitoring a wired communication link over an associated wireless communication link.

13. The method of claim 12 further including transmitting wired communication link statistics for a wired communication link that is terminated at a circuit element that hosts the associated wireless communication link.

14. A remote data acquisition device operable to wirelessly access computer system management data through an emulated device, wherein the remote data acquisition device comprises:

a processing module wherein firmware within the processing module represents the emulated device;

a first wireless tranceiver operable to wirelessly couple to a second wireless transceiver, wherein the second wireless transceiver is operably coupled to the computer system;

a multi-function integrated circuit, wherein the multi-function integrated circuit further comprises;

a floppy disk drive (FDD) interface operably coupled to a Bus Management Controller (BMC);

an FDD controller; and

server management hardware operable to write server management data to an emulated FDD.

15. The remote data acquisition device of claim 14, wherein the BMC further comprises General Purpose Input/Output (GPIO) pins to electrically couple to the FDD interface of the multi-function integrated circuit.

16. The remote data acquisition device of claim 14, wherein the BMC provides 13 signals to the FDD interface, and wherein the 13 signals provide the emulated FDD.

17. The remote data acquisition device server of claim 14, wherein the emulated FDD is a floppy “

B”

drive.

18. The remote data acquisition device of claim 14, wherein the server management data comprises fan tachometer outputs, temperature sensor outputs, ECC memory errors, storage subsystem statistics, firmware revisions, and/or unit ID information.

19. The remote data acquisition device of claim 14, wherein the server management data is represented within a virtual FAT file system.

20. The remote data acquisition device of claim 14, wherein the server management data is written to XML data files.