Optimization by using output drivers for discrete input interface

• US 20060190767A1
• Filed: 02/20/2005
• Published: 08/24/2006
• Est. Priority Date: 02/20/2005
• Status: Active Grant

• Current Assignee: Delphi Technologies Ip Limited (BorgWarner Incorporated)
• Original Assignee: Delphi Technologies, Inc. (Aptiv PLC)
• Inventors: Nair, Balakrishnan V.
• Granted Patent: US 7,502,963 B2
• Time in Patent Office: Days
• US Class Current: 714/25
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

The invention relates to design optimization of microprocessors using spare driver outputs for discrete input interfaces. An output driver or pre-FET driver is used to interface a discrete input for a microprocessor. To read the discrete interface, a fault detection mechanism of the pre-FET driver or the output driver is used. Monitoring the fault register of the output driver allows the condition of the external switch to be understood. The circuit is able to read either a switched to battery type interface or a switched to ground type interface, thereby eliminating hardware proliferation. The fault register is read through a serial peripheral interface (SPI) bus, thereby removing the need for a dedicated microprocessor pin required for the interface. Toggling the gate in the pre-FET driver interface permits adding diagnostic capability for the discrete input interface.

Claims

1. A method for design optimization of a processor to eliminate hardware proliferation using a processor having outputs with fault detection circuitry, comprising the steps of:

identifying a spare output of an output driver of the processor;

associating a serial peripheral interface and a desired input with the spare output; and

enabling the processor to access the fault detection circuitry of the spare output through the serial peripheral interface to determine an input value.

2. The method of claim 1 wherein the fault detection circuitry is adapted to be coupled to a switched to battery type interface.

3. The method of claim 1 wherein the fault detection circuitry is adapted to be coupled to a switched to ground type interface.

4. The method of claim 1 wherein the fault detection circuitry includes latch circuitry.

5. A method for design optimization of a processor to eliminate hardware proliferation using a processor having outputs with fault detection circuitry, comprising the steps of:

identifying a spare output of a pre-FET driver of the processor;

associating a serial peripheral interface and a desired input with the spare output; and

enabling the processor to determine an input value based on the fault detection circuitry through the serial peripheral interface of the pre-FET driver.

6. The method of claim 5 wherein the fault detection circuitry is adapted to be coupled to a switched to battery type interface.

7. The method of claim 5 wherein the fault detection circuitry is adapted to be coupled to a switched to ground type interface.

8. The method of claim 5 wherein the fault detection circuitry includes latch circuitry.

9. The method of claim 5, further comprising the step of toggling a gate in the pre-FET driver, thereby adding diagnostic capability.

10. A processor capable of utilizing outputs as input values comprising:

processing circuitry coupled to a plurality of outputs, at least one of said outputs including fault detection circuitry;

a serial peripheral interface coupled to a desired input;

a connection between said at least one output having fault detection circuitry and the desired input; and

means for determining the value of the desired input based on said serial peripheral interface and said connection.

11. The processor of claim 10 wherein said means for determining includes logic circuitry enabling a truth table.

12. The processor of claim 10 wherein said processing circuitry includes memory and said means for determining includes software stored in said memory.

13. The processor of claim 10 wherein said connection is adapted to be coupled to a switched to battery type interface.

14. The processor of claim 10 wherein said connection is adapted to be coupled to a switched to ground type interface.

15. The processor of claim 10 wherein said connection includes latch circuitry.