In-situ monitor of process and device parameters in integrated circuits

• US 20060190785A1
• Filed: 05/31/2005
• Published: 08/24/2006
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Pilling, David J.
• Granted Patent: US 7,594,149 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Claims

1. A scan path testing circuit embedded in an integrated circuit, comprising:

a test circuit embedded within the integrated circuit, the test circuit capable of providing data regarding at least one process, device, or circuit parameter;

an input register that provides an input signal to the test circuit; and

an output register that receives test data from the test circuit.

2. The scan path testing circuit of claim 1, wherein the test circuit is a resistance testing circuit.

3. The scan path testing circuit of claim 1, wherein the test circuit is a saturation current testing circuit.

4. The scan path testing circuit of claim 1, wherein the test circuit is a leakage current circuit.

5. The scan path testing circuit of claim 1, wherein the parameter testing circuit is a threshold voltage testing circuit.

6. The scan path testing circuit of claim 1, wherein the parameter test circuit is a delay line testing circuit.

7. The scan path testing circuit of claim 2, wherein the parameter test circuit determines a resistance value.

8. The scan path testing circuit of claim 1, wherein the parameter test circuit is a device monitoring circuit.

9. The scan path testing circuit of claim 1, wherein the input register is coupled to a digital-to-analog converter.

10. The scan path testing circuit of claim 1, wherein the output register is coupled to an analog-to-digital converter.

11. The scan path testing circuit of claim 1, wherein data in the output register is utilized to adjust operating parameters in the integrated circuit.

12. The scan path test of claim 1, wherein the test circuit is one of a group of test circuits included in a standard cell library.

13. The scan path test of claim 1, wherein the test circuit monitors the temperature on the integrated circuit.

14. A method of testing and monitoring an integrated circuit, comprising:

placing the integrated circuit in a test controller;

writing data to an input register in a scan path circuit with a test circuit; and

reading data from an output register of the scan path circuit, the output register being coupled to the test circuit.

15. The method of claim 14, wherein the test circuit is a leakage current test.

16. The method of claim 14, wherein the test circuit is a saturation current test.

17. The method of claim 14, wherein the test circuit is a threshold voltage test.

18. The method of claim 14, wherein the test circuit provides a device parameter.

19. The method of claim 14, wherein the test circuit determines a resistor value.

20. The method of claim 14, further including adjusting at least one parameter in the integrated circuit based on data read from the output register.