In-situ monitor of process and device parameters in integrated circuits

• US 20060190790A1
• Filed: 02/22/2005
• Published: 08/24/2006
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Pilling, David J., Talledo, Cesar
• Granted Patent: US 7,583,087 B2
• Time in Patent Office: Days
• US Class Current: 714/734
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Claims

1. An integrated circuit, comprising:

at least one test circuit embedded within the integrated circuit, the at least one test circuit capable of providing data regarding at least one process, device, or circuit parameter, the test circuit comprising;

a parameter testing circuit; and

an output driver coupled to receive a parameter signal from the parameter testing circuit.

2. The integrated circuit of claim 1, wherein the parameter test circuit further includes an input circuit coupled to provide at least one input signal to the parameter testing circuit.

3. The integrated circuit of claim 2, wherein the parameter testing circuit is a leakage testing circuit.

4. The integrated circuit of claim 2, wherein the parameter testing circuit is a resistance testing circuit.

5. The integrated circuit of claim 2, wherein the parameter testing circuit is a saturation current testing circuit.

6. The integrated circuit of claim 2, wherein the parameter testing circuit is a threshold voltage testing circuit.

7. The integrated circuit of claim 2, wherein the parameter test circuit is a delay line testing circuit.

8. The integrated circuit of claim 2, wherein the parameter test circuit determines a resistance value.

9. The integrated circuit of claim 2, wherein the parameter test circuit is a device monitoring circuit.

10. The integrated circuit of claim 2, wherein the input driver is coupled to a scan-path testing circuit.

11. The integrated circuit of claim 1, wherein the output driver is an analog-to-digital converter.

12. The integrated circuit of claim 1, wherein the output driver is coupled to an adjustment circuit that provides at least one adjusted parameter to the integrated circuit.

13. The integrated circuit of claim 11, wherein the analog-to-digital converter is coupled to an adjustment circuit that provides at least one adjusted parameter to the integrated circuit.

14. A method of testing and monitoring an integrated circuit, comprising:

placing the integrated circuit in a test controller;

providing input signals from the test controller to an input circuit in a test circuit embedded onto the integrated circuit;

monitoring output signals from the test circuit,

wherein the test circuit includes an input driver that receives the input signals from the test controller, a parameter test circuit coupled to the input driver to perform a parameter test, and an output driver coupled to receive signals from the parameter test circuit and provide an output signal to the test controller.

15. The method of claim 14, wherein the parameter test is a leakage current test.

16. The method of claim 14, wherein the parameter test is a saturation current test.

17. The method of claim 14, wherein the parameter test is a threshold voltage test.

18. The method of claim 14, wherein the parameter test provides a device parameter.

19. The method of claim 14, wherein the parameter test determines a resistor value.

20. The method of claim 14, wherein providing input signals and monitoring output signals includes interacting with a scan path testing circuit on the integrated circuit.

21. The method of claim 14, wherein providing input signals and monitoring output signals includes interacting with dedicated pins on the integrated circuit that are coupled to the input driver.

22. The method of claim 14, further including adjusting at least one parameter in the integrated circuit based on the output signals from the test circuit.

23. The method of claim 14, wherein providing input signals and monitoring output signals includes coupling to a scan path.

24. A method of monitoring an integrated circuit, comprising:

providing input signals to an input circuit in a test circuit embedded onto the integrated circuit;

monitoring output signals from the test circuit, wherein the test circuit includes an input driver that receives the input signals from the test controller, a parameter test circuit coupled to the input driver to perform a parameter test, and an output driver coupled to receive signals from the parameter test circuit and provide an output signal to the test controller; and

adjusting at least one parameter in the integrated circuit based on the output signals from the test circuit.

25. The method of claim 24, wherein the parameter test is a leakage current test.

26. The method of claim 24, wherein the parameter test is a saturation current test.

27. The method of claim 24, wherein the parameter test is a threshold voltage test.

28. The method of claim 24, wherein the parameter test determines a resistor value.

29. The method of claim 24, wherein the parameter test provides a device parameter.

30. The method of claim 24, wherein providing input signals and monitoring output signals includes interacting with a scan path testing circuit on the integrated circuit.

31. The method of claim 24, wherein the at least one parameter includes a current utilized in the integrated circuit.

32. The method of claim 24, wherein the at least one parameter includes a voltage utilized in the integrated circuit.

33. The method of claim 24, wherein providing input signals and monitoring output signals includes coupling to a scan path.