Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same

• US 20060190852A1
• Filed: 11/21/2005
• Published: 08/24/2006
• Est. Priority Date: 01/12/2005
• Status: Abandoned Application

• Current Assignee: Institute of Computer Science Foundation For Research and Technology- Hellas
• Original Assignee: Institute of Computer Science Foundation For Research and Technology- Hellas
• Inventors: Sotiriou, Christos P.
• Application Number:
  US11/283,070
• Publication Number:
  US 20060190852A1
• Time in Patent Office: Days
• US Class Current: 716/103
• CPC Class Codes: A45C 2003/007 Sport bags
• CPC Class Codes: A45C 5/14 with built-in rolling means
• CPC Class Codes: G06F 30/35 Delay-insensitive circuit design, e.g. asynchronous or self-timed
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00

Abstract

A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon'"'"'s expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

Claims

1. A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit, comprising:

converting the Boolean logic circuit into a first multi-rail circuit using at least Shannon'"'"'s expansion;

technology mapping the first multi-rail circuit into a second multi-rail circuit;

adding completion detection circuitry which receives the primary outputs of the second multi-rail circuit.

2. The method of claim 1, wherein as a result of said technology mapping the second multi-rail circuit is a combination of positive logic and negative logic.

3. The method of claim 1, wherein as a result of said adding the completion detection circuitry which receives only the primary outputs of the second multi-rail circuit.

4. The method of claim 1, wherein as a result of said adding the completion detection circuitry does receives any intermediate signals from the second multi-rail circuit.

5. The method of claim 1, wherein as a result of said adding the completion detection circuitry does receives any primary input signals from the second multi-rail circuit.

6. The method of claim 1, further comprising optimizing the first multi-rail circuit before said technology mapping.

7. The method of claim 1, further comprising optimizing the second multi-rail circuit before said adding.

8. The method of claim 1, further comprising optimizing at least the second multi-rail circuit after said adding.

9. The method of claim 1, further comprising:

dividing the second multi-rail circuit into m slices;

adding reset circuitry to at least a second slice of said m slices through an mth slice of said m slices, said circuitry being configured to receive a reset signal, such that a reset signal will simultaneously be applied to at least a second through an mth slice of said m slices.

10. The method of claim 9, wherein the reset signal is output by the completion detection circuitry.

11. The method of claim 1, further comprising:

propogating the completion detection signal upstream for use in the second multi-rail circuit; and

adding a delay to the completion detection signal;

propagating the delayed completion detection signal upstream of the second multi-rail circuit.