Efficient method for mapping a logic design on field programmable gate arrays

• US 20060190906A1
• Filed: 12/27/2005
• Published: 08/24/2006
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Sicronic Remote KG LLC (Intellectual Ventures LLC)
• Original Assignee: Sicronic Remote KG LLC (Intellectual Ventures LLC)
• Inventors: Agarwal, Viren, Samanta, Dhabalendu
• Granted Patent: US 7,676,782 B2
• Time in Patent Office: Days
• US Class Current: 716/116
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing the mapping time; and implementing a legalization adjustment to ensure mapping of said compensated design.

Claims

1. An efficient method for mapping a logic design on Field Programmable Gate Arrays comprising:

determining the minimum required square grid of FPGA logic blocks for mapping said design;

providing a compensation factor on said minimum square grids, and selecting the maximum value amongst said compensated square grids for reducing the placement time; and

implementing a legalization adjustment to ensure mapping of said compensated design.

2. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 1 wherein said determining comprises:

determining the minimum required number of FPGA logic blocks in a square grid for mapping corresponding design logic blocks;

determining the minimum required number of FPGA logic blocks in a square grid for mapping corresponding design Input/Output blocks; and

determining the minimum required number of FPGA logic blocks in a square grid for mapping corresponding design macros.

3. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 1 wherein said compensation factor for said square grid for said design logic blocks is calculated by multiplying said square grid for said design logic blocks by a factor ‘

X’

.

4. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 1 wherein said compensation factor of said square grid for said design Input/Output blocks is calculated by multiplying the number of Input/Output blocks with a factor ‘

Y’

.

5. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 1 wherein said compensation factor of said square grid for said design macros is calculated by multiplying the number of macro blocks with a factor ‘

Z’

.

6. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 3 wherein said factor ‘

X’

ranges between 1.5 to 3.

7. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 4 wherein said factor ‘

Y’

is 1 when more than one I/O logic block is held in Input/Output coordinate.

8. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 4 wherein said factor ‘

Y’

is 1.2 when Input/Output coordinate holds only one I/O logic block.

9. The efficient method for mapping a logic design on Field Programmable Gate Arrays as claimed in claim 5 wherein said factor ‘

Z’

is 1.2.