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Efficient method for mapping a logic design on field programmable gate arrays

  • US 20060190906A1
  • Filed: 12/27/2005
  • Published: 08/24/2006
  • Est. Priority Date: 12/29/2004
  • Status: Active Grant
First Claim
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1. An efficient method for mapping a logic design on Field Programmable Gate Arrays comprising:

  • determining the minimum required square grid of FPGA logic blocks for mapping said design;

    providing a compensation factor on said minimum square grids, and selecting the maximum value amongst said compensated square grids for reducing the placement time; and

    implementing a legalization adjustment to ensure mapping of said compensated design.

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