Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same
First Claim
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1. A semiconductor device, comprising:
- a semiconductor layer;
a first transistor in a first region of the semiconductor layer, the first transistor comprising;
a gate electrode that extends into the semiconductor layer in a vertical direction;
a source region and a drain region in the semiconductor layer arranged at opposite sides of the gate electrode in a horizontal direction; and
a lateral channel region of the semiconductor layer at a side of the gate electrode in a lateral direction that extends in the horizontal direction between the source region and the drain region; and
a second transistor in a second region of the semiconductor layer, the second transistor comprising a planar transistor.
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Abstract
In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
43 Citations
75 Claims
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1. A semiconductor device, comprising:
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a semiconductor layer;
a first transistor in a first region of the semiconductor layer, the first transistor comprising;
a gate electrode that extends into the semiconductor layer in a vertical direction;
a source region and a drain region in the semiconductor layer arranged at opposite sides of the gate electrode in a horizontal direction; and
a lateral channel region of the semiconductor layer at a side of the gate electrode in a lateral direction that extends in the horizontal direction between the source region and the drain region; and
a second transistor in a second region of the semiconductor layer, the second transistor comprising a planar transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of forming a semiconductor device, comprising:
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providing a first transistor in a first region of a semiconductor layer, comprising;
providing a cavity that extends in a vertical direction in the semiconductor layer;
providing a first gate dielectric at a lower portion and inner sidewalls of the cavity;
providing a gate electrode that fills a remaining portion of the cavity, the gate electrode extending in the vertical direction;
providing a source region and a drain region in the semiconductor layer that are arranged at opposite sides of the gate electrode in a horizontal direction; and
providing a lateral channel region of the semiconductor layer at a side of the gate electrode in a lateral direction that extends in the horizontal direction between the source region and the drain region; and
providing a second transistor in a second region of the semiconductor layer, the second transistor comprising a planar transistor. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A method of forming a semiconductor device comprising
defining a first active region and a second active region of a common semiconductor layer by using a first mask layer pattern and a second mask layer pattern, respectively; -
etching the first mask layer pattern in the first active region to reduce a width of the first mask layer pattern in a lateral direction by a first distance;
providing a third mask layer on the first active region to at least a level of the first mask layer pattern;
removing the first mask layer pattern in the first active region;
forming a vertical opening in a vertical direction of the semiconductor layer in the first active region using the third mask layer as an etch mask, sidewalls of the vertical opening having adjacent source and drain regions of the first active region in a horizontal direction and having at least one adjacent vertically oriented thin body channel region of the first active region along a sidewall of the vertical opening in the lateral direction;
providing a first gate dielectric on a bottom and the sidewalls of the vertical opening in the first active region;
providing a first gate electrode in a remaining portion of the opening on the gate dielectric in the first active region, to form a first transistor having the vertically oriented thin body channel region in the first active region;
removing the second mask layer to expose a surface of the semiconductor layer in the second active region;
providing a second gate dielectric on the semiconductor layer in the second active region; and
providing a second gate electrode on the second gate dielectric in the second active region, to form a second transistor in the second active region, the second transistor comprising a planar transistor. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
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Specification