Semiconductor device

• US 20060192282A1
• Filed: 02/24/2006
• Published: 08/31/2006
• Est. Priority Date: 02/25/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Suwa, Motoo, Betsui, Takafumi, Ikegami, Hikaru
• Granted Patent: US 7,745,915 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/181 associated with surface mounted components

Abstract

A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.

Claims

1. A semiconductor device comprising:

a mounting board; and

a plurality of semiconductor devices mounted over one surface of the mounting board,

wherein the mounting board has a plurality of substrate terminals formed in other surface thereof and wiring layers,

wherein the semiconductor devices each have a plurality of device terminals connected to the wiring layers of the mounting board,

wherein the semiconductor devices include a plurality of semiconductor memory devices operated in sync with a clock signal and a semiconductor data processing device for access-controlling the plurality of semiconductor memory devices,

wherein each of the semiconductor memory devices includes, as the device terminals, data input/output terminals, data strobe terminals, address input terminals and clock input terminals, and

wherein the semiconductor memory devices are disposed over the mounting board in such a manner that the data input/output terminals and the data strobe terminals are placed closer to the semiconductor data processing device than the address input terminals.

2. The semiconductor device according to claim 1,

wherein each of the semiconductor memory devices has a structure in which a synchronous DRAM chip having a double data rate is accommodated in a package having a terminal array based on the JEDEC standard, and

wherein the semiconductor data processing device has a structure in which a microcomputer chip is held in a chip size package.

3. The semiconductor device according to claim 1,

wherein the wiring layer of the mounting board has strobe signal wirings formed using areas among the mounted plural semiconductor memory devices, and

wherein the strobe signal wirings are wirings for connecting the data strobe terminals of the plural semiconductor memory devices to their corresponding terminals of the semiconductor data processing device.

4. The semiconductor device according to claim 3, further comprising:

data signal wirings for connecting the data input/output terminals of the plurality of semiconductor memory devices to their corresponding terminals of the semiconductor data processing device,

wherein the strobe signal wirings are disposed separately from the data signal wirings.

5. The semiconductor device according to claim 3,

wherein the wiring layer of the mounting board has a clock signal wiring formed using areas among the mounted plural semiconductor memory devices,

wherein the clock signal wiring is a wiring for connecting clock terminals of the plural semiconductor memory devices to their corresponding terminals of the semiconductor data processing device, and

wherein the clock signal wiring has stubs in midstream with the semiconductor data processing device as a base point and forms length-equalization paths extending to the respective semiconductor memory devices.

6. The semiconductor device according to claim 5, wherein the clock signal wiring is disposed separately from the data signal wirings and the strobe signal wirings.

7. The semiconductor device according to claim 5, wherein the clock signal wiring is configured by a differential pair.

8. The semiconductor device according to claim 7, wherein the substrate terminals has a pair of substrate terminals for connection of a differential terminating resistor connected to the stubs of the clock signal wiring.

9. The semiconductor device according to claim 8, wherein the pair of substrate terminals for connection of the differential terminating resistor adjoins each other.

10. The semiconductor device according to claim 8,

wherein the mounting board has a core layer and buildup layers formed in front and back surfaces thereof,

wherein the core layer has a power plane and a ground plane formed in the front and back surfaces thereof respectively,

wherein signal wirings for connecting the semiconductor memory devices and the semiconductor data processing device are formed using the wiring layers for the buildup layer on the mounted side of the semiconductor devices with respect to the core layer, and

wherein signal wirings for connecting the stubs to the corresponding substrate terminals for connection of the differential terminating resistor are formed using the wiring layers for the buildup layer on the formed side of the substrate terminals with respect to the core layer.

11. The semiconductor device according to claim 1, further including, as the substrate terminals, core power supply terminals for supplying a core-circuit power supply to the semiconductor data processing device, interface power supply terminals for supplying an external interface power supply to the semiconductor data processing device, memory power supply terminals for supplying a memory power supply to the semiconductor data processing device and the semiconductor memory devices, and ground terminals,

wherein the core power supply terminals are disposed close to the semiconductor data processing device,

wherein the memory power supply terminals are disposed close to the semiconductor memory devices, and

wherein the interface power supply terminals are dispersed around the mounting board together with signal terminals and ground terminals.

12. The semiconductor device according to claim 11, further including separately a first memory power supply terminal for supplying a first memory power supply used for memory operations of the semiconductor memory devices to the semiconductor memory devices, and a second memory power supply terminal for supplying a second memory power supply used for interface control on the semiconductor memory devices to the semiconductor data processing device.

13. The semiconductor device according to claim 12, wherein the mounting board has a first memory power plane connected to the first memory power supply terminal and a second memory power plane connected to the second memory power supply terminal separately, and

wherein the first memory power plane and the second memory power plane are formed in the wiring layers corresponding to layers different from each other and have layouts which overlap each other as viewed in the direction of front and back surfaces of the mounting board.

14. The semiconductor device according to claim 13, wherein the first memory power supply terminal and the second memory power supply terminal are disposed adjacent to each other.

15. The semiconductor device according to claim 13, wherein the second memory power plane has a layout superimposed, as viewed in the front/back surface direction of the mounting board, over signal wirings for connecting the data input/output terminals, data strobe terminals and clock input terminals of the semiconductor memory devices, and the device terminals corresponding to those terminals, of the semiconductor data processing device.

16. The semiconductor device according to claim 15,

wherein the mounting board has a core layer and buildup layers formed in front and back surfaces thereof,

wherein signal wirings for connecting the semiconductor memory devices and the semiconductor data processing device are formed using the wiring layers for the buildup layer on the implemented side of the semiconductor devices with respect to the core layer,

wherein the core layer has a power plane and a ground plane formed in the front and back surfaces thereof,

wherein the second power plane is formed in part of a layer for forming the power plane, and

wherein the first power plane is formed using the wiring layer for the buildup layer adjacent to the power plane forming layer as viewed in a front/back surface direction thereof.

17. The semiconductor device according to claim 11, further including, as the substrate terminals, a first reference potential terminal for supplying a reference potential to the semiconductor memory devices, and a second reference potential terminal for supplying a reference potential to the semiconductor data processing device,

wherein the mounting board has a memory power plane connected to the memory power supply terminals, and

wherein the first reference potential terminal and the second reference potential terminal have layouts superimposed over the memory power plane as viewed in the front/back surface direction of the mounting board.

18. The semiconductor device according to claim 17, wherein the first reference potential terminal and the second reference potential terminal are disposed adjacent to the memory power supply terminals and the ground terminals.

19. The semiconductor device according to claim 18,

wherein the substrate terminals have layouts in which plural rows are concentrically turned around, and

wherein the first reference potential terminal and the second reference potential terminal are placed in an innermost periphery of a turned-around disposed substrate terminal array.

20. The semiconductor device according to claim 11,

wherein the semiconductor data processing device has a PLL circuit or a DLL circuit and has power supply device terminals and ground device terminals dedicated to the PLL circuit or DLL circuit as its device terminals,

wherein the mounting board has substrate power supply terminals and substrate ground terminals dedicated to the PLL circuit or DLL circuit as substrate terminals, and

wherein within a plane vertical to the front/back surface direction of the mounting board, the power supply substrate terminals are positioned in the neighborhood of the power supply device terminals, and the ground substrate terminals are positioned in the neighborhood of the ground device terminals.

21. The semiconductor device according to claim 20, wherein the power supply substrate terminals and the ground substrate terminals are adjacent to one another.

22. The semiconductor device according to claim 1,

wherein the substrate terminals include a turned-around terminal group in which plural rows are concentrically turned around, and a central terminal group surrounded by the turned-around terminal group, and

wherein test-dedicated terminals connected to the corresponding device terminals of the semiconductor memory devices are allocated to part of the central terminal group and part of terminals on the inner periphery side of the turned-around terminal group.

23. The semiconductor device according to claim 22,

wherein an input terminal for a clock enable signal for indicating the validity of a signal inputted to the clock input terminal is provided as the device terminal of each of the semiconductor memory devices,

wherein an output terminal for outputting the clock enable signal is provided as the device terminal of the semiconductor data processing device, and

wherein a terminal connected to the input terminal for the clock enable signal and a terminal connected to the output terminal for the clock enable signal are provided separately as the substrate terminals.

24. The semiconductor device according to claim 23, wherein the substrate terminal connected to the input terminal for the clock enable signal, and the substrate terminal connected to the output terminal for the clock enable signal are disposed adjacent to each other.

25. A semiconductor device comprising:

a mounting board; and

a plurality of semiconductor devices mounted over one surface of the mounting board,

wherein the mounting board has a plurality of substrate terminals formed in other surface thereof and wiring layers,

wherein the semiconductor devices respectively have a plurality of device terminals connected to the wiring layers of the mounting board,

wherein the semiconductor devices include a plurality of semiconductor memory devices operated in sync with a clock signal and a semiconductor data processing device for access-controlling the plurality of semiconductor memory devices, as the plurality of semiconductor devices,

wherein core power supply terminals for supplying a core-circuit power supply to the semiconductor data processing device, interface power supply terminals for supplying an external interface power supply to the semiconductor data processing device, memory power supply terminals for supplying a memory power supply to the semiconductor data processing device and the semiconductor memory devices, and ground terminals are provided as the substrate terminals,

wherein the core power supply terminals are disposed close to the semiconductor data processing device,

wherein the memory power supply terminals are disposed close to the semiconductor memory devices, and

wherein the interface power supply terminals are dispersed around the mounting board together with signal terminals.

26. A semiconductor device comprising:

a mounting board; and

a plurality of semiconductor devices mounted over one surface of the mounting board,

wherein the mounting board has a plurality of substrate terminals formed in other surface thereof and wiring layers,

wherein the semiconductor devices respectively have a plurality of device terminals connected to the wiring layers of the mounting board,

wherein the semiconductor devices include a plurality of semiconductor memory devices operated in sync with a clock signal and a semiconductor data processing device for access-controlling the plurality of semiconductor memory devices, as the plurality of semiconductor devices,

wherein memory power supply terminals for supplying a memory power supply to the semiconductor data processing device and the semiconductor memory devices, ground terminals, a first reference potential terminal for supplying a reference potential to the semiconductor memory devices, and a second reference potential terminal for supplying a reference potential to the semiconductor data processing device,

wherein the mounting board has a memory power plane connected to the memory power supply terminals, and

wherein the first reference potential terminal and the second reference potential terminal have layouts superimposed over the memory power plane as viewed in the direction of front and back surfaces of the mounting board.

27. A semiconductor device comprising:

a mounting board; and

a plurality of semiconductor devices mounted over one surface of the mounting board,

wherein the mounting board has a plurality of substrate terminals formed in other surface thereof and wiring layers,

wherein the semiconductor devices respectively have a plurality of device terminals connected to the wiring layers of the mounting board,

wherein the semiconductor devices include a plurality of semiconductor memory devices operated in sync with a clock signal and a semiconductor data processing device for access-controlling the plurality of semiconductor memory devices, as the plurality of semiconductor devices,

wherein the semiconductor data processing device has a PLL circuit or a DLL circuit and has power supply device terminals and ground device terminals dedicated to the PLL circuit or DLL circuit as its device terminals,

wherein the mounting board has substrate power supply terminals and substrate ground terminals dedicated to the PLL circuit or DLL circuit as substrate terminals, and

wherein within a plane vertical to the front/back surface direction of the mounting board, the power supply substrate terminals are positioned in the neighborhood of the power supply device terminals, and the ground substrate terminals are positioned in the neighborhood of the ground device terminals.