Integrated connection arrangements

• US 20060192289A1
• Filed: 02/09/2006
• Published: 08/31/2006
• Est. Priority Date: 08/14/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Korner, Heinrich, Mitchell, Andrea, Klein, Wolfgang, Goebel, Thomas, Hommel, Martina, Helneder, Johann, Schwerd, Markus, Drexl, Stefan, Seck, Martin
• Granted Patent: US 7,619,309 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

Claims

1. An integrated circuit connection arrangement, comprising:

an electrically conductive outer conductive structure being arranged at least partly in a cutout of an electrically insulating insulation layer, the outer conductive structure having at least one edge region adjoining the insulating layer outside the cutout;

an electrically conductive inner conductive structure being arranged at a bottom of the cutout toward a first side of the cutout and adjoining the outer conductive structure at a bottom of the cutout in a contact zone; and

a contact area arranged at the outer conductive structure on a second side of the cutout,

where the contact zone does not overlap the contact area in a direction normal to an area of the inner conductive structure adjoining the contact zone, the bottom of the cutout, in the normal direction, overlapping at least half of the contact area.

2. The integrated circuit connection arrangement of claim 1, comprising an edge of the cutout at a distance from a main current path of the outer conductive structure arranged between the contact area and the inner conductive structure, the edge of the cutout unrestrictive to the main current path, and arranged outside the main current path.

3. The integrated circuit connection arrangement of claim 2, where the distance is at least about 10 nm.

4. The integrated circuit connection arrangement of claim 1, where the outer conductive structure comprises an interconnect configured for lateral current flow in a metallization stratum in a first section.

5. The integrated circuit connection arrangement of claim 4, where a length of the first section is at least about 10 nm.

6. The integrated circuit connection arrangement of claim 1, where the outer conductive structure projects beyond the contact zone at a side of the inner conductive structure being remote from the section with the contact area.

7. The integrated circuit connection arrangement of claim 6, where the outer conductive structure projects beyond the contact zone by at least about 10 nm.

8. The integrated circuit connection arrangement of claim 1, where the inner conductive structure comprises a metallization stratum having interconnects configured for lateral current flow in the metallization stratum.

9. The integrated circuit connection arrangement of claim 1, where the outer conductive structure comprises a connection area providing an external connection arrangement.

10. The integrated circuit connection arrangement of claim 9, where the outer conductive structure comprises a connection area providing a bonding connection.

11. The integrated circuit connection arrangement of claim 1, where the inner conductive structure comprises a damascened-formed conductive structure having a main conductive body with at least about a 90% copper mass ratio, and the outer conductive structure includes a main conductive body of aluminum having at least about a 90% aluminum mass ration and a barrier layer at the contact zone, where the barrier layer includes a layer of any one of tantalum, titanium, titanium nitride, tantalum nitride, or a layer sequence of any combination thereof.

12. The integrated circuit connection arrangement of claim 1, where the outer conductive structure comprises a passivation layer substantially covering the outer conductive layer in at least one edge region along a periphery of the contact area.

13. The integrated circuit connection arrangement of claim 11, where the passivation comprises a layer of any one of a silicon dioxide layer, a silicon nitride layer or combination silicon dioxide layer and a silicon nitride layer.

14. The integrated circuit connection arrangement of claim 1, where the outer conductive structure includes at least one edge region adjoining the insulation layer outside the cutout proximate an edge region extending around the cutout.

15. The integrated circuit connection arrangement of claim 1, where the contact zone comprises a planar zone, the integrated circuit arrangement being arranged in a semiconductor substrate carrying a plurality of integrated semiconductor components in a main area.

16. A method for producing an integrated circuit arrangement having a connection arrangement, the method comprising:

forming a plurality of components in a main area of a substrate;

producing an inner metallization stratum with a plurality of inner conductive structures, at least one inner conductive structure being formed as an interconnect conducting current parallel to the main area during operation of the circuit arrangement;

adjoining the inner metallization stratum of an outer metallization stratum with a plurality of outer conductive structures, at least one outer conductive structure adjoining an inner conductive structure in a contact zone;

forming a contact area at the outer conductive structure;

where the contact zone does not substantially overlap the contact area in a direction normal to the area of the inner conductive structure that adjoins the contact zone, and the contact zone in the normal direction being configured to overlap at least half of the contact area.

17. The method of claim 16, comprising forming at least one outer conductive structure as an interconnect which conducts current parallel to the main area during operation of the circuit arrangement.

18. The method of claim 17, further comprising producing the inner metallization stratum using a damascene technique with a subsequent planarization step, and producing the outer metallization stratum by depositing a layer and subsequently patterning the layer using a photolithography.

19. An integrated circuit arrangement, comprising:

a plurality of components in a main area of a substrate;

an inner metallization stratum having a plurality of inner conductive structures, at least one inner conductive structure configured as an interconnect conducting current parallel to the main area, where the inner metallization stratum adjoins a plurality of outer conductive structures, at least one outer conductive structure adjoining an inner conductive structure in a contact zone;

a contact area at the outer conductive structure;

where the contact zone does not substantially overlap the contact area in a direction normal to the area of the inner conductive structure that adjoins the contact zone, and the contact zone in the normal direction being configured to overlap at least half of the contact area.

20. The integrated circuit arrangement of claim 19, comprising at least one outer conductive structure configured as an interconnect conducting current parallel to the main area during operation of the circuit arrangement.

21. The integrated circuit arrangement of claim 19, where the inner metallization stratum comprises a damascene-formed stratum, and the outer metallization stratum includes a photolithography-formed layer.