Manufacturing method for electronic device

• US 20060192299A1
• Filed: 02/20/2006
• Published: 08/31/2006
• Est. Priority Date: 02/25/2005
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hashimoto, Nobuaki
• Application Number:
  US11/358,894
• Publication Number:
  US 20060192299A1
• Time in Patent Office: Days
• US Class Current: 257/782
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/25175 Parallel arrangements
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82007 involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2224/82101 by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387

Abstract

A manufacturing method for electronic device, includes: forming a first interconnection on a substrate; disposing a pedestal having a predetermined shape on the substrate; and forming a second interconnection connecting to the first interconnection, extending onto the pedestal.

Claims

1. A manufacturing method for electronic device, comprising:

forming a first interconnection on a substrate;

disposing a pedestal having a predetermined shape on the substrate; and

forming a second interconnection connecting to the first interconnection, extending onto the pedestal.

2. A manufacturing method for electronic device according to claim 1, further comprising:

forming a sloping face at least part of a side face of the pedestal, wherein the sloping face slopes with respect to a top face of the substrate.

3. A manufacturing method for electronic device according to claim 2, wherein a sloping angle of the sloping face with respect to the top face of the substrate is an acute angle.

4. A manufacturing method for electronic device according to claim 1, wherein the forming of the second interconnection includes:

forming a seed layer on the substrate and the pedestal;

coating a resist on the seed layer;

forming an opening in the resist in a region on which the second interconnection is formed, and exposing the seed layer;

forming the second interconnection by plating the seed layer;

removing the resist; and

removing the seed layer by using the second interconnection as a mask.

5. A manufacturing method for electronic device according to claim 4, wherein the forming of the second interconnection includes:

forming a first layer of the second interconnection by plating the seed layer; and

forming a second layer of the second interconnection by plating the first layer.

6. A manufacturing method for electronic device according to claim 1, wherein the forming of the second interconnection includes:

performing a process of silane coupling on the substrate and the pedestal;

forming a residual pattern of a silane coupling film corresponding to an interconnection pattern of the second interconnection;

forming a seed layer on the residual pattern of the silane coupling film on the substrate and the pedestal; and

forming the second interconnection by plating the seed layer.

7. A manufacturing method for electronic device according to claim 1, further comprising:

preparing an electronic component having an electrode face with electrodes formed thereon;

facing a top face of the pedestal and the electrode face of the electronic component;

connecting the electrodes to the second interconnection extending onto the pedestal; and

electrically connecting the first interconnection to the electrodes of the electronic component with the second interconnection therebetween.

8. A manufacturing method for electronic device according to claim 7, wherein at least additional pedestal is disposed on the pedestal, and the electronic component is disposed on the additional pedestal.

9. A manufacturing method for electronic device according to claim 7, wherein the electronic component includes an IC chip.

10. A manufacturing method for electronic device according to claim 1, further comprising:

preparing an electronic component having an electrode face with electrodes formed thereon and a back rear on an opposite side to the electrode face;

facing a top face of the pedestal and the back rear of the electronic component;

fixing the electronic component on the top face of the pedestal;

forming an insulating section having a sloping face sloping with respect to the top face of the pedestal, on at least part of a side of the electronic component;

forming the second interconnection extending from the first interconnection to the electrodes with the sloping face of the insulating section therebetween; and

electrically connecting the first interconnection to the electrodes of the electronic component with the second interconnection therebetween.

11. A manufacturing method for electronic device according to claim 10, wherein at least additional pedestal is disposed on the pedestal, and the electronic component is disposed on the additional pedestal.

12. A manufacturing method for electronic device according to claim 10, wherein a sloping angle of the sloping face with respect to the top face of the pedestal is an acute angle.

13. A manufacturing method for electronic device according to claim 10, wherein the electronic component includes an IC chip.