Shredded parallel stacked inductor

• US 20060192645A1
• Filed: 02/15/2006
• Published: 08/31/2006
• Est. Priority Date: 02/15/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae-sup, Lee, Seong-soo, Kim, Sung-nam
• Granted Patent: US 7,515,027 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields

Abstract

A shredded parallel stacked inductor is provided. The shredded parallel stacked inductor includes a substrate, an oxide film formed on the substrate, metallic layers spirally formed within the oxide film, and vias formed in regions of the metallic layers to join the metallic layers in parallel, thus forming a spiral cavity in a center part of the metallic layers.

Claims

1. A shredded parallel stacked inductor comprising:

a substrate;

an oxide film formed on the substrate;

a plurality of metallic layers spirally formed within the oxide film; and

a plurality of vias formed in regions of the plurality of metallic layers to join the plurality of metallic layers in parallel,

wherein a spiral cavity is formed in the plurality of metallic layers.

2. The shredded parallel stacked inductor as claimed in claim 1, wherein the regions are proximal parts of the plurality of metallic layers.

3. The shredded parallel stacked inductor as claimed in claim 1, wherein the regions are distal parts of the plurality of metallic layers.

4. The shredded parallel stacked inductor as claimed in claim 1, wherein the regions are corner parts of the plurality of metallic layers.

5. The shredded parallel stacked inductor as claimed in claim 1, wherein the spiral cavity is formed in a center part of the plurality of metallic layers except for at the proximal and distal parts of the metallic layers.

6. The shredded parallel stacked inductor as claimed in claim 1, wherein a current depletion layer of each of the plurality of the metallic layers is reduced by the spiral cavity when electric current is applied to the inductor.

7. The shredded parallel stacked inductor as claimed in claim 1, wherein the shredded parallel stacked inductor has a structure stacked in parallel by the vias.

8. The shredded parallel stacked inductor as claimed in claim 1, wherein long sides of the plurality of metallic layers have a length of about 10 μ

m, and short sides of the plurality of metallic layers have a length of about 3 μ

m.