Thin film transistor array panel and manufacturing method thereof

• US 20060192906A1
• Filed: 02/17/2006
• Published: 08/31/2006
• Est. Priority Date: 02/25/2005
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Oh, Min-Seok, Kim, Sang-Gab, Kim, Shi-Yul, Ryu, Hye-Young, Chin, Hong-Kee, Choe, Hee-Hwan, Kim, Jang-Soo
• Granted Patent: US 8,305,507 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2202/02 organic material

Abstract

A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

Claims

1. A thin film transistor array panel, comprising:

a gate line;

a data line intersecting the gate line;

a storage electrode apart from the gate line and the data line;

a thin film transistor connected to the gate line and the data line and having a drain electrode;

a pixel electrode connected to the drain electrode;

a first insulating layer over the thin film transistor and disposed under the pixel electrode; and

a second insulating layer disposed on the first insulating layer, and having an opening exposing the first insulating layer on the storage electrode.

2. The thin film transistor array panel of claim 1, wherein the first insulating layer is made of inorganic material.

3. The thin film transistor array panel of claim 2, wherein the second insulating layer is made of organic material.

4. The thin film transistor array panel of claim 3, wherein the second insulating layer includes a color filter.

5. The thin film transistor array panel of claim 1, wherein the storage electrode is made of the same layer as the gate line.

6. The thin film transistor array panel of claim 1, wherein a contact hole to connect the pixel electrode and the drain electrode is disposed in the opening.

7. The thin film transistor array panel of claim 1, further comprising:

a shielding electrode made of the same layer as the pixel electrode.

8. The thin film transistor array panel of claim 7, wherein the shielding electrode and the pixel electrode are disposed on the first insulating layer and the second insulating layer.

9. The thin film transistor array panel of claim 8, wherein the storage electrode is made of the shielding electrode, and is extended from the shielding electrode.

10. The thin film transistor array panel of claim 9, wherein the storage electrode overlaps the drain electrode.

11. The thin film transistor array panel of claim 7, wherein the shielding electrode is extended to the data line.

12. The thin film transistor array panel of claim 11, wherein the shielding electrode completely covers the boundaries of the data line.

13. The thin film transistor array panel of claim 7, wherein the shielding electrode overlaps at least a portion of the gate line.

14. The thin film transistor array panel of claim 13, wherein the shielding electrode is extended to the data line and the gate line.

15. The thin film transistor array panel of claim 14, wherein the width of the shielding electrode is larger than that of the data line and smaller than that of the gate line.

16. The thin film transistor array panel of claim 1, wherein the pixel electrode has a cutout.

17. The thin film transistor array panel of claim 1, wherein the pixel electrode includes a first pixel electrode and a second pixel electrode coupled with the first pixel electrode.

18. The thin film transistor array panel of claim 17, further comprising:

a coupling electrode connected to the drain electrode and overlapping the second pixel electrode,

wherein the coupling electrode overlaps the second pixel electrode only via the first insulating layer.

19. A thin film transistor array panel, comprising:

a gate line formed on an insulating substrate;

a gate insulating layer formed on the gate line;

a first semiconductor formed on the gate insulating layer;

a data line and a drain electrode formed on the first semiconductor, the data line and the drain electrode being separate from each other;

a storage conductor formed on the gate insulating layer;

a first passivation layer formed on the storage conductor, the data line, and the drain electrode;

a second passivation layer formed on the first passivation layer and having an opening exposing the first passivation layer corresponding to the storage conductor; and

a pixel electrode connected to the drain electrode on the second passivation layer overlapping the storage conductor through the opening.

20. The thin film transistor array panel of claim 19, wherein the first passivation layer is thinner than the second passivation layer.

21. The thin film transistor array panel of claim 19, wherein the first passivation layer includes inorganic material or the second passivation layer includes organic material.

22. The thin film transistor array panel of claim 19, further comprising a second semiconductor made at the same layer as the first semiconductor, and disposed under the storage conductor.

23. The thin film transistor array panel of claim 19, wherein the first semiconductor, except for a portion between the data line and the drain electrode, has the same plane shape as the data line and the drain electrode.

24. The thin film transistor array panel of claim 19, wherein the first semiconductor is made of amorphous silicon.

25. The thin film transistor array panel of claim 19, further comprising:

a shielding electrode formed on the second passivation layer and overlapping at least a portion of the gate line and the data line.

26. The thin film transistor array panel of claim 25, wherein the first passivation layer and the second passivation layer have a contact hole exposing the storage conductor, and the storage conductor is connected to the shielding electrode through the contact hole.

27. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on an insulating substrate;

forming a gate insulating layer over the gate line;

forming a semiconductor on the gate insulating layer;

forming an ohmic contact layer on the semiconductor;

forming a data line, a drain electrode apart from the data line, and a storage conductor on the ohmic contact layer;

forming first and second passivation layers covering the data line, the drain electrode, and the storage conductor;

etching the first and second passivation layers to form a contact hole exposing the drain electrode and an opening exposing the first passivation layer corresponding to the storage conductor; and

forming a pixel electrode connected to the drain electrode through the contact hole and overlapping the storage conductor through the opening.

28. The method of claim 27, wherein the semiconductor, the data line, the drain electrode, and the storage conductor are formed by photolithography using one photoresist film as an etch mask.