Non-volatile and static random access memory cells sharing the same bitlines

• US 20060193174A1
• Filed: 02/25/2005
• Published: 08/31/2006
• Est. Priority Date: 02/25/2005
• Status: Abandoned Application

• Current Assignee: O2ic, Inc.
• Original Assignee: O2IC
• Inventors: Kwon, Eui Pil, Choi, David S., Choi, Kyu Hyun
• Application Number:
  US11/067,313
• Publication Number:
  US 20060193174A1
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.

Claims

1. A memory structure comprising:

a first MOS transistor having a first current carrying terminal directly coupled to a first node, a second current carrying terminal directly coupled to a first bitline associated with the memory structure, and a gate terminal directly coupled to a first terminal of the memory structure;

a second MOS transistor having a first current carrying terminal directly coupled to the first node, a gate terminal directly coupled to a second node, and a second current carrying terminal adapted to receive a first voltage;

a first non-volatile memory cell comprising;

a first substrate region directly coupled to a second terminal of the memory structure;

a source region formed in the first substrate region and directly coupled to the first bitline;

a drain region formed in the first substrate region and separated from the source region by a first channel region;

said drain region being directly coupled to a third terminal of the memory structure;

a first gate overlaying a first portion of the first channel region and separated therefrom via a first insulating layer;

said first gate directly coupled to a fourth terminal of the memory structure; and

a second gate overlaying a second portion of the first channel region and separated therefrom via a second insulating layer;

wherein said first portion of the first channel region and said second portion of the first channel region do not overlap and wherein said second gate is directly coupled to a fifth terminal of the memory structure;

said first non-volatile memory cell being adapted so as not to include a floating gate disposed between said first and second gates thereof;

a third MOS transistor having a first current carrying terminal directly coupled to the second node, a second current carrying terminal directly coupled to a second bitline associated with the memory structures, and a gate terminal directly coupled to the first terminal of the memory structure;

a fourth MOS transistor having a first current carrying terminal directly coupled to the second node, a gate terminal directly coupled to the first node, and a second current carrying terminal adapted to receive the first voltage; and

a second non-volatile memory cell comprising;

a second substrate region directly coupled to the second terminal of the memory structure;

a source region formed in the second substrate region and directly coupled to the second bitline associated with the memory structure;

a drain region formed in the second substrate region and separated from the source region of the second substrate region by a second channel region;

said drain region of the second substrate region being directly coupled to the third terminal of the memory structure;

a first gate overlaying a first portion of the second channel region and separated therefrom via a first insulating layer and directly coupled to the fourth terminal of the memory structure; and

a second gate overlaying a second portion of the second channel region and separated therefrom via a second insulating layer, wherein said first portion of the second channel region and said second portion of the second channel region do not overlap and wherein said second gate overlaying the second portion of the second channel region is directly coupled to the fifth terminal of the memory structure, said second non-volatile memory cell being adapted so as not to include a floating gate disposed between said first and second gates thereof.

2. The memory structure of claim 1 wherein the first and second nodes receive their respective voltages from the first and second bitlines and maintain their respective voltages after the fist and second MOS transistors are turned off.

3. The memory structure of claim 2 wherein the second terminal of the memory structure is adapted to receive the first voltage, the third terminal of the memory structure is adapted to receive a second voltage, the fourth terminal of the memory structure is adapted to receive a third supply voltage, and the fifth terminal of the memory structure is adapted to receive a fourth supply voltage.

4. The memory structure of claim 3 wherein the fourth voltage is greater than the first, second, and third voltages.

5. The memory structure of claim 4 wherein the first voltage is 0 volt.

6. The memory structure of claim 4 wherein during a write cycle one of the first and second non-volatile memory cells traps more electrons in its nitride layer than does the other one of the first and second non-volatile memory cells.

7. The memory structure of claim 6 wherein the electrons are trapped via hot-electron injection.

8. The memory structure of claim 6 wherein the electrons are trapped via tunneling.

9. The memory structure of claim 8 wherein after the write cycle, the first voltage is applied to the first and second terminals, the second voltage is applied to the third and fifth input terminals, and a fifth voltage is applied to the fourth terminal, wherein the fifth voltage is smaller than the second voltage.

10. The memory structure of claim 9 wherein the trapped electrons are untrapped by applying the first voltage to first second and third terminals of the memory structure, applying a negative voltage to the fifth terminal of the memory structure and by enabling the fourth terminal of the memory structure to float.

11. The memory structure of claim 10 wherein said first and second non-volatile memory cells are operated in subthreshold regions.

12. The memory structure of claim 3 wherein the fist terminal of the memory structure is adapted to receive the second voltage.

13. The memory structure of claim 12 wherein the first and second nodes receive voltages from the first and second non-volatile memory cells respectively via the first and second bitlines.

14. The memory structure of claim 1 wherein said memory structure is disposed in a memory array.

15. The memory structure of claim 13 wherein said memory structure is a redundant memory structure disposed in a memory array and for repair use.

16. The memory structure of claim 1 wherein said first and second MOS transistors are periodically turned on.

17. The memory structure of claim 1 wherein said memory cell includes at least one resistive load.

18. The memory structure of claim 1 wherein said memory structure includes more than one pair of non-volatile memory cells and or more than one SRAM cell attached to the same bitline.

19. The memory structure of claim 13 wherein voltages applied to the said memory structure are applied at the same time the same voltages are applied to another memory structure within the memory array.

20. The memory structure of claim 14 wherein the non-volatile memory cells are adjacent to non-volatile memory cells of the other memory structures in the memory array.