Semiconductor device with a plurality of fuse elements and method for programming the device

• US 20060193185A1
• Filed: 02/17/2006
• Published: 08/31/2006
• Est. Priority Date: 02/17/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takai, Tomohisa
• Granted Patent: US 7,330,383 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 17/143 using laser-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/802 by encoding redundancy signals
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses

Abstract

A device and method for programming the semiconductor device that includes a plurality of first fuse-sets which store first information, wherein each of the first fuse-sets includes at least one first fuse element and the first information has been compressed, a second fuse-set including at least one second fuse element which stores data modification information used to modify the first information and an information creation circuit which modifies the first information based on the data modification information, expands the modified first information and thereby creates second information.

Claims

1. A semiconductor device comprising:

a first fuse-set configured to represent first information, wherein the first fuse-set includes at least one first fuse element having a state that represents whether the first information has been compressed; and

a second fuse-set configured to represent second information, wherein the second fuse set includes at least one second fuse element having a state that represents data modification information for modifying the first information represented in the first fuse set.

2. The semiconductor device according to claim 1, further comprising:

an information creation circuit configured to modify the first information based on the data modification information and further expand the first information after being modified by the data modification information to create the second information.

3. The semiconductor device according to claim 1, wherein a first fuse of the first fuse-set is configured to store a first enable bit indicative of whether data stored in the first fuse-set has been compressed.

4. The semiconductor device according to claim 3, wherein the information creation circuit is configured to modify the first enable bit based on the data modification information.

5. The semiconductor device according to claim 4, wherein the second fuse-set is configured to store an indicator bit which indicates that the first enable bit stored in the first fuse-set is modified.

6. The semiconductor device according to claim 5, wherein the information creation circuit is configured to modify the first enable bit stored in the first fuse-set which the indicator bit is of a first predetermined state.

7. The semiconductor device according to claim 3, wherein:

the first fuse-set stores an address bit indicative of an address of a defective cell in a memory cell array replaced by a spare cell in a spare memory cell array; and

the second fuse-set stores a second enable bit which sets an operation mode of the information creation circuit.

8. The semiconductor device according to claim 7, the information creation circuit is configured to modify the first enable bit based on the data modification information when the second enable bit indicates a first operation mode, and the information creation circuit modifies the address bit based on the data modification information when the second enable bit indicates a second operation mode.

9. A semiconductor device comprising:

a memory cell array having a plurality of memory cells;

a spare memory cell array having a plurality of spare cells available to compensate for a detective cell in the memory cell array;

a first fuse-set configured to represent first redundancy information used to replace the defective cell by a spare cell of the plurality of spare cells in the spare memory cell array, wherein the first fuse-set includes at least one first fuse element having a state that represents whether the first redundancy information has been compressed; and

a second fuse-set configured to represent second information, wherein the second fuse set includes at least one second fuse element having a state that represents data modification information for modifying the first information represented in the first fuse set.

10. The semiconductor device according to claim 9, further comprising:

an information creation circuit configured to modify the first information based on the data modification information and further expand the first information after being modified by the data modification information to create the second information

11. The semiconductor device according to claim 10, wherein a first fuse of the first fuse-set is configured to store a first enable bit indicative of whether whether data stored in the first fuse-set has been compressed

12. The semiconductor device according to claim 11, wherein the information creation circuit is configured to modify the first enable bit based on the data modification information.

13. The semiconductor device according to claim 12, wherein the second fuse-set is configured to store an indicator bit which indicates that the first enable bit stored in the first fuse-sets is modified.

14. The semiconductor device according to claim 13, wherein the information creation circuit is configured to modify the first enable bit stored in the first fuse-set which the indicator bit is of a first predetermined state.

15. The semiconductor device according to claim 11, wherein the first fuse-set stores an address bit indicative of an address of a defective cell in a memory cell array replaced by a spare cell in a spare memory cell array;

and

the second fuse-set stores a second enable bit which sets an operation mode of the information creation circuit.

16. The semiconductor device according to claim 15, the information creation circuit is configured to modify the first enable bit based on the data modification information when the second enable bit indicates a first operation mode, and the information creation circuit modifies the address bit based on the data modification information when the second enable bit indicates a second operation mode.

17. A semiconductor device comprising:

a memory having a cell with an address;

a first fuse set;

means for determining if said cell is defective;

means for representing first information with the first fuse set, including means for representing whether the first information has been compressed, said first information including the address of the cell when said first information is not compressed;

means for determining if there is an error in the means for representing whether the first information has been compressed; and

means for modifying the first information with data modification information when the means for representing includes the error.

18. A method for setting states of fuse elements in a semiconductor device, comprising steps of

determining if a cell in a memory is defective;

setting an address of a replacement cell for saving in a first fuse set when in said determining step it is determined that said memory cell is defective;

including first information indicative of whether the address has been compressed;

determining if there is an error in the first information; and

modifying the first information with data modification information when an error has been determined to exist in the first information.

19. The method according to claim 18, wherein said setting step includes programming the first fuse set with the address and the first information.

20. The method according to claim 18, wherein said modifying step includes checking a state of a fuse in a second set of fuses against the first information to determine how to correct said error.