Communication of conversation between terminasl over a radio link

• US 20060193269A1
• Filed: 03/15/2004
• Published: 08/31/2006
• Est. Priority Date: 03/27/2003
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Perraud, Eric, Comps, Christopher
• Granted Patent: US 8,213,343 B2
• Time in Patent Office: Days
• US Class Current: 370/278
• CPC Class Codes: H04M 1/6066 including a wireless connection
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements
• CPC Class Codes: H04W 52/0216 using a pre-established activity schedule, e.g. traffic indication frame
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A package device has one integrated circuit in a cavity in a package substrate and electrically coupled to one side of the package substrate. A second integrated circuit is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit or more may be mounted on the second integrated circuit. Pads useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

Claims

1. A method of forming a package device, comprising;

providing a package substrate having a first side and a second side and having first pads on the first side and second pads on the second side;

placing a first integrated circuit on the first side and a second integrated circuit on a second side;

electrically connecting the first integrated circuit to the first pads and the second integrated circuit to the second pads; and

testing the first integrated circuit and the second integrated circuit by applying test probes to the first pads and the second pads.

2. A method for forming a package device, comprising:

providing a package substrate having a first surface along a first plane and second surface along a second plane, wherein the package substrate has a cavity between the first plane and the second plane;

placing a first integrated circuit in the cavity;

placing a second integrated circuit adjacent to the first integrated circuit outside the cavity; and

depositing encapsulating material over the first integrated circuit and the second integrated circuit.

3. The method of claim 2, wherein the step of depositing comprises:

depositing a first portion of the encapsulating material over the first integrated circuit prior to the step of placing the second integrated circuit; and

depositing a second portion of the encapsulating material over the second integrated circuit.

4. The method of claim 2, wherein the package substrate further comprises a supporting member along the second plane of the substrate.

5. The method of claim 4, further comprising removing the supporting member prior to step of placing the second integrated circuit.

6. A package device, comprising:

a package substrate having a first surface defining a first plane and a second surface defining a second plane, the package substrate having a cavity between the first plane and the second plane;

a first integrated circuit in the cavity; and

a second integrated circuit, coupled to the package substrate, outside the cavity.

7. A package device, comprising:

a package substrate having a first side and a second side;

first pads on the first side;

second pads on the second side;

a first integrated circuit mounted to the package substrate;

wherein the first pads and the second pads are further characterized as being useful for receiving test probes for testing.

8. The package device of claim 7, further comprising a second integrated circuit mounted to the package substrate.

9. The package device of claim 8, wherein:

the first integrated circuit is electrically connected to the first pads; and

the second integrated circuit is electrically connected to the second pads.

10. The package device of claim 9, wherein the substrate is further characterized as having a cavity and the first integrated circuit is further characterized as being in the cavity.