Methods for assembling semiconductor devices and interposers

• US 20060194373A1
• Filed: 04/25/2006
• Published: 08/31/2006
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Edmund Lua Koon Tian, Eric Tan Swee Seng, Keith Tan, Leng Nam Yin, Lim Thiam Chye, Patrick Guay, Setho Sing Fee, Steven W. Heppler, Yap Kah Eng
• Original Assignee: Edmund Lua Koon Tian, Eric Tan Swee Seng, Keith Tan, Leng Nam Yin, Lim Thiam Chye, Patrick Guay, Setho Sing Fee, Steven W. Heppler, Yap Kah Eng
• Inventors: Tan, Keith, Chye, Lim Thiam, Fee, Setho Sing, Heppler, Steven W., Seng, Eric Tan Swee, Guay, Patrick, Yin, Leng Nam, Eng, Yap Kah, Tian, Edmund Lua Koon
• Granted Patent: US 7,528,007 B2
• Time in Patent Office: Days
• US Class Current: 438/125
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a retention element that extends over at least a portion of the receptacle. Material may be introduced between at least a portion of an outer periphery of the one or more semiconductor devices and an inner periphery of the interposer to facilitation securing of the one or more semiconductor devices in place relative to the interposer. The retention element may be removed from the semiconductor devices. Once the one or more semiconductor devices are in place, they may be electrically connected to the interposer.

Claims

1. A method for assembling semiconductor device components, comprising

providing an interposer with a substantially planar substrate comprising semi conductive material, a receptacle formed substantially through the substantially planar substrate, and a film at least partially covering an opening of the receptacle;

positioning at least one semiconductor device within the receptacle and securing the at least one semiconductor device to the film.

2. The method of claim 1, further comprising:

introducing encapsulant material between at least a portion of an outer periphery of the at least one semiconductor device and a periphery of the receptacle.

3. The method of claim 2, wherein introducing encapsulant material comprises introducing encapsulant material in contact with an active surface of the at least one semiconductor device.

4. The method of claim 3, wherein introducing encapsulant material comprises substantially covering the active surface of the at least one semiconductor device.

5. The method of claim 2, wherein introducing encapsulant material comprises substantially filling space remaining within the receptacle.

6. The method of claim 2, wherein introducing encapsulant material comprises at least partially confining the at least one semiconductor device within the receptacle.

7. The method of claim 2, further comprising:

removing the film following introducing encapsulant material.

8. The method of claim 1, wherein positioning comprises positioning a backside of the at least one semiconductor device against the film.

9. The method of claim 1, wherein positioning comprises positioning a plurality of semiconductor devices within the receptacle.

10. The method of claim 1, further comprising:

electrically connecting the at least one semiconductor device to the interposer.

11. The method of claim 10, wherein electrically connecting comprises positioning an

intermediate conductive element between at least one bond pad of the at least one semiconductor device and a corresponding contact area of the interposer.

12. The method of claim 11, wherein positioning the intermediate conductive element comprises connecting a bond wire between the at least one bond pad and the corresponding contact area.

13. The method of claim 10, further comprising:

testing the at least one semiconductor device and an electrical connection between the at least one semiconductor device and the interposer; and

attaching the semiconductor device to the interposer.

14. The method of claim 1, further comprising:

placing a conductive structure on at least one terminal of the interposer.

15. A method for assembling semiconductor device components, comprising:

positioning at least one semiconductor device within a receptacle that extends substantially through of an interposer, on a retention element extending over at least a portion of the receptacle.

16. The method of claim 15, wherein positioning comprises positioning the at least one semiconductor device on a retention element that is secured to a surface of the interposer.

17. The method of claim 15, wherein positioning comprises positioning the at least one semiconductor device on a retention element comprising a film.

18. The method of claim 15, further comprising:

securing the at least one semiconductor device to the retention element.

19. The method of claim 15, further comprising:

introducing material between at least a portion of an outer periphery of the at least one semiconductor device and at least a portion of an inner periphery of the receptacle to facilitate retention of the at least one semiconductor device within the receptacle.

20. The method of claim 19, wherein introducing comprises introducing encapsulant material.

21. The method of claim 19, further comprising:

removing the retention element following the act of introducing.

22. The method of claim 15, further comprising:

electrically connecting the at least one semiconductor device to the interposer.