Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process

• US 20060194401A1
• Filed: 02/28/2005
• Published: 08/31/2006
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pendharkar, Sameer P., Hu, Binghua, Ramirez, Joseph M., Wofford, Bill A.
• Granted Patent: US 7,435,659 B2
• Time in Patent Office: Days
• US Class Current: 438/369
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/708 Mark formation
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

Claims

1. A method for manufacturing a semiconductor device having an alignment feature, comprising;

implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate;

oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2;

1 or greater;

removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

2. The method as recited in claim 1 wherein implanting an n-type dopant into a substrate thereby forming an implanted region includes implanting an n-type dopant using a dose of about 1E15 atoms/cm² or greater.

3. The method as recited in claim 2 wherein implanting an n-type dopant into a substrate using a dose of about 1E15 atoms/cm² or greater includes implanting using an energy of about 30 KeV or greater.

4. The method as recited in claim 2 wherein the dose is about 1E16 atoms/cm² or greater.

5. The method as recited in claim 2 further including subjecting the implanted region to a drive step after oxidizing the substrate using the wet oxidation process, thereby forming a deep n-type well having a surface concentration less than about 1E19 atoms/cm³.

6. The method as recited in claim 5 wherein the deep n-type well functions as a contact region for a collector portion of a bipolar transistor.

7. The method as recited in claim 5 further including forming trench isolation structures proximate the alignment feature, the trench isolation structures having a step height of about 60 nm or less.

8. The method as recited in claim 7 wherein forming trench isolation structures includes forming trench isolation structures without any additional masks or special moat processing steps.

9. The method as recited in claim 1 wherein oxidizing the substrate using a wet oxidation process includes oxidizing the substrate using a low temperature wet oxidation process using a temperature ranging from about 850°

C. to about 1000°

C.

10. The method as recited in claim 1 wherein removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region includes leaving an alignment feature self-aligned to the implanted region.

11. The method as recited in claim 1 wherein the n-type dopant is phosphorous.

12. The method as recited in claim 11 wherein the ratio is about 3:

1 or greater.

13. The method as recited in claim 1 wherein the n-type dopant is selected from the group consisting of antimony and arsenic.

14. The method as recited in claim 1 wherein the substrate is epitaxial silicon.