Canceling harmonics in semiconductor RF switches

• US 20060194558A1
• Filed: 02/03/2006
• Published: 08/31/2006
• Est. Priority Date: 02/03/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Kelly, Dylan J.
• Granted Patent: US 8,081,928 B2
• Time in Patent Office: Days
• US Class Current: 455/319
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

An RF switching circuit adapted to cancel selected harmonic signals. An unwanted harmonic signal Sh1 at a selected harmonic frequency Fsh of an operating frequency Fo exists in a signal Si conducted by the switching circuit, possibly produced by the switching circuit due to conduction through a first nonlinear impedance Znl(1). A compensating harmonic signal Sh2 is therefore generated by conduction via a nonlinear impedance Znl(2). Znl(1) may be due to parasitic conduction by “off” switching elements, while Znl(2) may be due to conduction by an “on” FET. The amplitude and/or phasing of Sh2 may be adjusted by selecting components for a network coupling Znl(2) to the conducted signal Si, such that Sh2 substantially cancels Sh1 across a target range of input power.

Claims

1. A method of canceling unwanted harmonic signal component Sh1 at a frequency Fsh that is a selected harmonic of an operating frequency Fo of a signal Sc that is conducted by an integrated semiconductor RF signal switching circuit along a signal conduction path Psc from an input node Nin to an output node Nout, the method comprising:

a) conducting a compensation current Icc between Psc and an AC reference voltage vref via a compensation nonlinear impedance Znlc;

b) developing a compensating harmonic signal Sh2 at the frequency Fsh as a component of Sc due to conduction of Icc through an impedance;

c) wherein Sh2 has a phase and amplitude at Fsh related to a phase and amplitude of Sh1 at Fsh such that a sum of Sh1 plus Sh2 has a lower amplitude at Fsh than does Sh1 alone, across a target range of Sc amplitude.

2. The method of claim 1, wherein developing Sh2 in step (b) is primarily due to conducting Icc through an equivalent impedance of the conducted signal Sc.

3. The method of claim 1, wherein Znlc is a compressive nonlinear impedance that increases with increasing current.

4. The method of claim 3, wherein Znlc is a characteristic of a channel of an FET that is biased “

on.”

5. The method of claim 4, wherein Znlc is an output device in a driver circuit configured to bias “

off”

a switching element in an unselected alternative signal conduction path coupled to Nout.

6. The method of claim 1, further comprising generating the unwanted harmonic signal Sh1 by coupling a distortion current path Pdi, which includes a nonlinear distortion impedance Znld, between Psc and vref.

7. The method of claim 6, wherein unselected signal switching elements, including one or more FETs that are biased “

off,”

substantially establish the nonlinear impedance Znld of the distortion path Pdi.

8. The method of claim 6, wherein Znlc and Znld have significantly different nonlinear characteristics.

9. The method of claim 8, wherein one of Znld and Znlc is substantially reactive, while the other of Znld and Znlc is substantially resistive.

10. The method of claim 1, further comprising controlling the phase and amplitude of Sh2 by causing Icc to be conducted via a phase control path Ppc that establishes a frequency-dependent impedance pole or zero within three octaves of Fsh.

11. A monolithic RF signal switching integrated circuit comprising:

a) an input node Nin configured to receive an input signal Si having an amplitude Pin at an operating frequency Fo;

b) a signal conduction path Psc that is selectable to couple the input signal Si at Nin to an output node Nout via a switching element including a channel of a transistor controllably biased to an “

on”

state as an output signal So; and

c) compensation circuitry configured to generate a harmonic compensation signal Sch to cancel part of an unwanted harmonic distortion signal Sdh from So, the compensation circuitry including a compensation signal path Psc that conducts current from Si to an AC reference voltage vref via a compensating nonlinear impedance element Znlc.

12. The integrated circuit of claim 11, wherein current through the compensation signal path Psc via Znlc is compensation current Icc, and the harmonic compensation signal Sch is primarily a product of Icc with an equivalent impedance Zi of the input signal Si expected to be received at Nin.

13. The integrated circuit of claim 11, wherein an impedance magnitude of Znlc increases with increasing current.

14. The integrated circuit of claim 13, wherein Znlc includes nonlinear conduction by an FET that is biased “

on.”

15. The integrated circuit of claim 11, wherein the input signal Si is expected to have an equivalent input impedance Zi, further comprising (d) a distortion current path Pdi disposed between Psc and vref, which in operation conducts a distorted current Id from Psc that induces the harmonic distortion signal Sdh as a product of Id*Zi.

16. The integrated circuit of claim 15, wherein the distortion of current path Pdi is due to a nonlinear distortion impedance Znld of Pdi, and Znld has a much different phase than the compensating nonlinear impedance Znlc at Fsh

17. The integrated circuit of claim 16, further comprising one or more unselected signal conduction paths including FETs, and having nonlinear impedances that together substantially establish Znld from the impedance of one or more FETs that are biased “

off”

, and Znlc is substantially due to an impedance of one or more FETs that are biased “

on.”

18. The integrated circuit of claim 11, wherein the compensation signal path Psc further comprises a phase-magnitude control circuit having a frequency-dependent impedance pole or zero at a selected corner frequency that is within three octaves of a selected frequency Fsh that is a harmonic of the operating frequency Fo.

19. The integrated circuit of claim 11, further comprising a plurality of controllable conduction path switch elements that each include a multiplicity of FETs stacked in series and biased on or off together.

20. An integrated circuit apparatus for coupling RF signals from a selectable one of a. plurality of input nodes including Nin to an output node Nout, comprising:

a) means for inducing an unwanted harmonic signal Sh1 onto an input signal coupled to Nout; and

b) compensation means for inducing a compensating harmonic signal Sh2 onto the input signal coupled to Nout, such that a magnitude of (Sh1+Sh2) is lower at a selected harmonic frequency Fsh for a target range of amplitude of the input signal, the compensation means including a compensation signal path Psc that is configurable to conduct a compensation current Icc from Nout to a reference voltage vref via a nonlinear compensation impedance Znlc.