Digital filter instruction and filter implementing the filter instruction

• US 20060195498A1
• Filed: 02/28/2005
• Published: 08/31/2006
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: Hwang, Kirk, Dobbek, Jeffrey J.
• Granted Patent: US 8,117,248 B2
• Time in Patent Office: Days
• US Class Current: 708/300
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: H03H 17/02 Frequency selective networks digital computers for complex mathematical operations G06F17/10
• CPC Class Codes: H03H 2017/0298 DSP implementation

Abstract

A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Claims

1. A filter instruction for synthesizing a digital filter, wherein the filter instruction is executed by a machine, the filter instruction comprising an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit.

2. The filter instruction of claim 1, wherein the fields designate memory locations in a circular buffer.

3. The filter instruction of claim 1, wherein the clear accumulator bit is used for clearing a memory location storing an accumulated value before filter computation.

4. The filter instruction of claim 1, wherein the update bit is used for saving the accumulator value in a memory location for storing an accumulated value.

5. The filter instruction of claim 1, wherein the tap length field is used to define the number of taps for the filter.

6. The filter instruction of claim 1, wherein the coefficient address provides the coefficient address pointer.

7. The filter instruction of claim 1, wherein the data address field provides the data address pointer.

8. The filter instruction of claim 1, wherein the clear accumulator bit is set to a first value and the update bit is set to a first value to configure the processor to evaluate an n tap filter to produce an output value, the output value being maintained in an accumulator memory location and to update an offset of a data header address.

9. The filter instruction of claim 1, wherein the clear accumulator bit is set to a second value and the update bit is set to a first value to configure the processor to clear an accumulator memory location before evaluating the n tap filter and to update an offset of a data header address.

10. The filter instruction of claim 1, wherein the clear accumulator bit is set to a first value and the update bit is set to a second value to configure the processor to evaluate an n tap filter to produce an output value, to save the output value into a table at an accumulator memory location and to update an offset of a data header address.

11. The filter instruction of claim 1, wherein the clear accumulator bit is set to a second value and the update bit is set to a second value to configure the processor to clear an accumulator memory location before evaluating an n tap filter to produce an output value, to save the output value into a table the an accumulator memory location and to update an offset of a data header address.

12. The filter instruction of claim 1, wherein the filter instruction causes the sum of the data values and corresponding coefficient values to be stored in an accumulator memory location.

13. The filter instruction of claim 1, wherein the filter instruction updates a header of a circular buffer with a new offset which points to a next entry for a new input sample to be stored, the computation and updating of the data pointer being performed without a branch penalty.

14. An apparatus comprising:

a processor having registers, the processor configured to implement a digital filter based upon a filter instruction;

addressable memory coupled to the processor for storing input, coefficient and output data, the addressable memory configured as a circular buffer; and

a filter instruction executable on the processor to implement the digital filter, the filter instruction comprising an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit.

15. The apparatus of claim 14, wherein the fields designate memory locations in a circular buffer.

16. The apparatus of claim 14, wherein the clear accumulator bit is used for clearing a memory location storing an accumulated value before filter computation.

17. The apparatus of claim 14, wherein the update bit is used for saving the accumulator value in a memory location for storing an accumulated value.

18. The apparatus of claim 14, wherein the tap length field is used to define the number of taps for the filter.

19. The apparatus of claim 14, wherein the coefficient address provides the coefficient address pointer.

20. The apparatus of claim 14, wherein the data address field provides the data address pointer.

21. The apparatus of claim 14, wherein the clear accumulator bit is set to a first value and the update bit is set to a first value to configure the processor to evaluate an n tap filter to produce an output value, the output value being maintained in an accumulator memory location and to update an offset of a data header address.

22. The apparatus of claim 14, wherein the clear accumulator bit is set to a second value and the update bit is set to a first value to configure the processor to clear an accumulator memory location before evaluating the n tap filter and to update an offset of a data header address.

23. The apparatus of claim 14, wherein the clear accumulator bit is set to a first value and the update bit is set to a second value to configure the processor to evaluate an n tap filter to produce an output value, to save the output value into a table at an accumulator memory location and to update an offset of a data header address.

24. The apparatus of claim 14, wherein the clear accumulator bit is set to a second value and the update bit is set to a second value to configure the processor to clear an accumulator memory location before evaluating an n tap filter to produce an output value, to save the output value into a table the an accumulator memory location and to update an offset of a data header address.

25. The apparatus of claim 14, wherein the filter instruction causes the sum of the data values and corresponding coefficient values to be stored in an accumulator memory location.

26. The apparatus of claim 14, wherein the filter instruction updates a header of a circular buffer with a new offset which points to a next entry for a new input sample to be stored, the computation and updating of the data pointer being performed without a branch penalty.

27. A magnetic storage device, comprising:

a magnetic storage medium for recording data thereon;

a motor for moving the magnetic storage medium;

a head for reading and writing data on the magnetic storage medium;

an actuator for positioning the head relative to the magnetic storage medium; and

a data channel for processing encoded signals on the magnetic storage medium, the data channel comprising;

a processor having registers, the processor configured to implement a digital filter based upon a filter instruction; and

addressable memory coupled to the processor for storing input, coefficient and output data, the addressable memory configured as a circular buffer;

wherein the processor is configurable to provide a digital filter according to a filter instruction, the filter instruction comprising an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit.

28. The magnetic storage device of claim 27, wherein the fields designate memory locations in a circular buffer.

29. The magnetic storage device of claim 27, wherein the clear accumulator bit is used for clearing a memory location storing an accumulated value before filter computation.

30. The magnetic storage device of claim 27, wherein the update bit is used for saving the accumulator value in a memory location for storing an accumulated value.

31. The magnetic storage device of claim 27, wherein the tap length field is used to define the number of taps for the filter.

32. The magnetic storage device of claim 27, wherein the coefficient address provides the coefficient address pointer.

33. The magnetic storage device of claim 27, wherein the data address field provides the data address pointer.

34. The magnetic storage device of claim 27, wherein the clear accumulator bit is set to a first value and the update bit is set to a first value to configure the processor to evaluate an n tap filter to produce an output value, the output value being maintained in an accumulator memory location and to update an offset of a data header address.

35. The magnetic storage device of claim 27, wherein the clear accumulator bit is set to a second value and the update bit is set to a first value to configure the processor to clear an accumulator memory location before evaluating the n tap filter and to update an offset of a data header address.

36. The magnetic storage device of claim 27, wherein the clear accumulator bit is set to a first value and the update bit is set to a second value to configure the processor to evaluate an n tap filter to produce an output value, to save the output value into a table at an accumulator memory location and to update an offset of a data header address.

37. The magnetic storage device of claim 27, wherein the clear accumulator bit is set to a second value and the update bit is set to a second value to configure the processor to clear an accumulator memory location before evaluating an n tap filter to produce an output value, to save the output value into a table the an accumulator memory location and to update an offset of a data header address.

38. The magnetic storage device of claim 27, wherein the filter instruction causes the sum of the data values and corresponding coefficient values to be stored in an accumulator memory location.

39. The magnetic storage device of claim 27, wherein the filter instruction updates a header of a circular buffer with a new offset which points to a next entry for a new input sample to be stored, the computation and updating of the data pointer being performed without a branch penalty.