Method to detect NAND-flash parameters by hardware automatically

• US 20060195650A1
• Filed: 02/25/2005
• Published: 08/31/2006
• Est. Priority Date: 02/25/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Liu, Hongping, Su, Zhiqiang J., Lan, Hui, Shami, Qasim R.
• Granted Patent: US 7,657,696 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification

Abstract

A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.

Claims

1. A method for automatically detecting a plurality of parameters for a NAND-Flash memory, comprising the steps of:

(A) generating a plurality of address cycles for said NAND-Flash memory;

(B) setting an address number parameter of said parameters based on (i) a first number of said address cycles generated and (ii) a status signal generated by said NAND-Flash memory responsive to said address cycles;

(C) generating at least one read cycle for said NAND-Flash memory after determining said address number parameter; and

(D) setting a page size parameter of said parameters based on (i) a second number of said read cycles generated and (ii) said status signal further responsive to said read cycles.

2. The method according to claim 1, further comprising the step of:

generating a first command cycle for said NAND-Flash memory prior to generating said address cycles.

3. The method according to claim 2, further comprising the step of:

setting a command sequence parameter of said parameters to a first type in response to (i) said address number parameter having a predetermined value and (ii) said status signal transitioning to a busy state after a last of said address cycles.

4. The method according to claim 3, further comprising the step of:

generating a second command cycle for said NAND-Flash memory in response to said status signal remaining in a ready state after said last address cycle.

5. The method according to claim 4, further comprising the step of:

setting said command sequence parameter to a second type in response to said status signal transitioning to said busy state after said first command cycle.

6. The method according to claim 1, further comprising the step of:

asserting a signal after determining said parameters.

7. The method according to claim 6, further comprising the step of:

booting a processor from said NAND-Flash memory in response to said assertion of said signal.

8. The method according to claim 7, further comprising the step of:

copying a first page from said NAND-Flash memory to a memory.

9. The method according to claim 8, further comprising the step of:

executing from said memory upon completing said copying.

10. The method according to claim 9, further comprising the steps of:

copying a second page from said NAND-Flash memory to said memory in response to said processor accessing an instruction stored in said second page of said NAND-Flash memory and not in said memory;

error correcting said instruction copied from said NAND-Flash memory; and

executing said instruction from said memory.

11. A system comprising:

a NAND-Flash memory; and

a controller circuit configured to (i) generate a plurality of address cycles for said NAND-Flash memory, (ii) set an address number parameter of said parameters based on (a) a first number of said address cycles generated and (b) a status signal generated by said NAND-Flash memory responsive to said address cycles, (iii) generate at least one read cycle for said NAND-Flash memory after determining said address number parameter and (iv) set a page size parameter of said parameters based on (i) a second number of said read cycles generated and (ii) said status signal further responsive to said read cycles.

12. The system according to claim 11, wherein said controller circuit is further configured to generate a first command cycle for said NAND-Flash memory prior to generating said address cycles.

13. The system according to claim 12, wherein said controller circuit is further configured to set a command sequence parameter of said parameters to a first type in response to (i) said address number parameter having a predetermined value and (ii) said status signal transitioning to a busy state after a last of said address cycles.

14. The method system to claim 13, wherein said controller circuit is further configured to generate a second command cycle for said NAND-Flash memory in response to said status signal remaining in a ready state after said last address cycle.

15. The system according to claim 14, wherein said controller circuit is further configured to set said command sequence parameter to a second type in response to said status signal transitioning to said busy state after said first command cycle.

16. The system according to claim 11, wherein said controller circuit consists of a hardware-only circuit.

17. The system according to claim 11, further comprising a processor in communication with said controller circuit to receive said parameters for said NAND-Flash memory.

18. The system according to claim 17, wherein:

said controller circuit is further configured to inform said processor when said parameters are available; and

said processor is further configured to boot directly from said NAND-Flash memory.

19. The system according to claim 11, wherein said controller circuit is further configured to determine a bus width parameter of said parameters in response to both a read enable signal and data read from said NAND-Flash memory.

20. A system comprising:

a NAND-Flash memory;

a controller circuit implemented as hardware-only and configured to determine a plurality of parameters for said NAND-Flash memory; and

a processor configured to boot from said NAND-Flash memory based on said parameters.