Semiconductor component and method of manufacture

• US 20060197154A1
• Filed: 03/03/2005
• Published: 09/07/2006
• Est. Priority Date: 03/03/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pelella, Mario M., Chan, Simon S., Chan, Darin A.
• Granted Patent: US 7,223,640 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a Semiconductor-on-Insulator (SOI) substrate having a major surface, the SOI substrate comprising a first layer of semiconductor material, a layer of dielectric material disposed on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material;

forming a first active semiconductor device from the first layer of semiconductor material; and

forming a second active semiconductor device from the second layer of semiconductor material.

2. The method of claim 1, wherein forming the first active semiconductor device includes forming an analog semiconductor device.

3. The method of claim 2, wherein forming the analog semiconductor device comprises forming the analog semiconductor device as a portion of an analog circuit selected from the group of analog circuits consisting of a phase-locked loop circuit, an input-output circuit, sense amplifiers, an electro-static discharge protection circuit, and a sensor circuit.

4. The method of claim 1, further including forming an electrical contact to the first layer of semiconductor material.

5. The method of claim 4, wherein forming the electrical contact includes forming a first shallow trench that extends through the second layer of semiconductor material and the layer of dielectric material.

6. The method of claim 5, wherein forming the first shallow trench includes extending the first shallow trench into the first layer of semiconductor material.

7. The method of claim 5, further including forming a second shallow trench that extends through the second layer of semiconductor material and the layer of dielectric material, the second shallow trench laterally spaced apart from the first shallow trench.

8. The method of claim 7, wherein forming the second shallow trench includes extending the second shallow trench into the first layer of semiconductor material.

9. The method of claim 8, further including forming semiconductor material of a first conductivity type in the first and second shallow trenches.

10. The method of claim 9, wherein forming the semiconductor material in the first and second shallow trenches includes epitaxially growing the semiconductor material in the first and second shallow trenches.

11. The method of claim 10, wherein forming the semiconductor material in the first and second shallow trenches includes forming a first portion of the semiconductor material in the first shallow trench to have a first dopant concentration and a second portion of the semiconductor material in the first shallow trench to have a second dopant concentration.

12. The method of claim 11, wherein the first dopant concentration is greater than the second dopant concentration, and wherein the first portion of the semiconductor material contacts the second layer of semiconductor material.

13. The method of claim 11, further including forming a first portion of the semiconductor material in the second shallow trench to have a third dopant concentration and a second portion of the semiconductor material in the second shallow trench to have a fourth dopant concentration.

14. The method of claim 13, wherein the first and third dopant concentrations are substantially the same and the second and fourth dopant concentrations are substantially the same.

15. The method of claim 13, further including forming first and second shallow trench isolation structures in the second layer of semiconductor material, wherein the first shallow trench isolation structure extends from the major surface to the first layer of dielectric material and the second shallow trench isolation structure extends from the major surface through the first semiconductor material in the first shallow trench to the portion of the first semiconductor material having the first dopant concentration.

16. The method of claim 15, wherein forming the electrical contact comprises:

forming a trench in the semiconductor material filling the second shallow trench, the trench extending from the first major surface to the portion of the first semiconductor material having the first dopant concentration;

forming a dielectric material in the trench;

forming an opening in the dielectric material, the opening extending to the portion of the first semiconductor material having the first dopant concentration; and

forming an electrically conductive material in the opening.

17. The method of claim 16, wherein forming the electrically conductive material in the opening includes selecting the electrically conductive material from the group of electrically conductive materials consisting of tungsten, an alloy of tungsten, titanium, an alloy of titanium, tantalum, an alloy of tantalum, copper, an alloy of copper, aluminum, and an alloy of aluminum.

18. The method of claim 15, wherein forming the electrical contact comprises:

forming a trench in the semiconductor material filling the second shallow trench, the trench extending from the first major surface to the portion of the first semiconductor material having the first dopant concentration; and

doping a portion of the semiconductor material filling the second shallow trench with an impurity material of the first conductivity type.

19. The method of claim 18, wherein doping the portion of the semiconductor material filling the second shallow trench includes doping the portion to have an impurity concentration of at least about 1×

10¹⁶ atoms per centimeter cubed.

20. The method of claim 18, further including forming a silicide layer from the portion of the semiconductor material filling the second shallow trench.

21. A method for manufacturing a semiconductor component, comprising:

providing a Semiconductor-on-Insulator (SOI) substrate having a major surface, the SOI substrate comprising a first layer of semiconductor material, a layer of dielectric material disposed on the first layer of semiconductor material, and a second layer of semiconductor material disposed on the layer of dielectric material;

forming first and second trenches in the SOI substrate, the first and second trenches laterally spaced apart from each other and extending from the major surface into the first layer of semiconductor material;

forming first and second epitaxial semiconductor materials in the first and second trenches, respectively, wherein a portion of the first epitaxial semiconductor material in the first trench contacts the first layer of semiconductor material and has a first dopant concentration and a portion of the first epitaxial semiconductor material in the first trench that is spaced apart from the first layer of semiconductor material has a second dopant concentration and wherein a portion of the second epitaxial semiconductor material in the second trench contacts the first layer of semiconductor material and has a first dopant concentration and a portion of the second epitaxial semiconductor material that is spaced apart from the first layer of semiconductor material has a second dopant concentration;

forming a first semiconductor device from the portion of the first epitaxial semiconductor material in the first trench; and

forming a second semiconductor device from a portion of the second layer of semiconductor material.

22. The method of claim 21, further including forming a substrate contact from the second epitaxial semiconductor material in the second trench.

23. The method of claim 22, wherein forming the substrate contact includes:

forming a trench in the second epitaxial semiconductor material in the second trench;

forming a dielectric material in the trench in the second epitaxial semiconductor material;

forming an opening in the dielectric material in the trench in the second epitaxial semiconductor material; and

forming an electrically conductive material in the opening.

24. The method of claim 23, wherein the electrically conductive material is selected from the group of electrically conductive materials consisting of titanium, tungsten, copper, aluminum, and doped semiconductor material.

25. The method of claim 22, wherein forming the substrate contact includes doping a portion of the second epitaxial semiconductor material in the second trench with an impurity material of the first conductivity type.

26. The method of claim 21, wherein forming the first semiconductor device includes doping a portion of the second epitaxial semiconductor material in the second trench with an impurity material of the first conductivity type;

forming a first trench in the second layer of semiconductor material and the layer of dielectric material, wherein the trench exposes a portion of the first layer of semiconductor material;

forming the first epitaxial semiconductor material in the first trench;

forming a gate structure on the first epitaxial semiconductor material, the gate structure having first and second sides; and

forming a source region in the first epitaxial semiconductor material adjacent the first side of the gate structure and a drain region in the first epitaxial semiconductor material adjacent the second side of the gate structure.

27. A semiconductor component, comprising:

a Semiconductor-on-Insulator (SOI) substrate having a major surface, the SOI substrate comprising a first layer of semiconductor material, a layer of dielectric material disposed on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material;

a first epitaxial semiconductor material extending from the first layer of semiconductor material;

a second epitaxial semiconductor material extending from another portion of the first layer of semiconductor material, the first and second epitaxial semiconductor materials electrically isolated from each other;

a first active semiconductor device disposed on the first epitaxial semiconductor material; and

a second active semiconductor device disposed on the second layer of semiconductor material.

28. The semiconductor component of claim 27, further including a substrate contact formed from the second epitaxial semiconductor material.

29. The semiconductor component of claim 28, wherein the second epitaxial semiconductor material has a first portion doped with a dopant of a first concentration and a second portion doped with a dopant of a second concentration, the second portion disposed on the first portion and the second concentration less than the first concentration.

30. The semiconductor component of claim 29, wherein the substrate contact comprises a doped region formed in the second portion of the second epitaxial layer, the doped region having a greater dopant concentration than the second portion of the second epitaxial layer.

31. The semiconductor component of claim 29, wherein the substrate contact comprises a dielectric material extending through the second portion of the second epitaxial layer and a trench extending through the dielectric material, wherein the trench is filled with an electrically conductive material that contacts the first layer of semiconductor material.