Method of fabricating wafer-level packaging with sidewall passivation and related apparatus

• US 20060197190A1
• Filed: 04/21/2006
• Published: 09/07/2006
• Est. Priority Date: 01/29/2004
• Status: Active Grant

• Current Assignee: Trung T. Doan
• Original Assignee: Trung T. Doan
• Inventors: Doan, Trung T.
• Granted Patent: US 7,656,012 B2
• Time in Patent Office: Days
• US Class Current: 257/620
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1191 Forming a passivation layer after forming the bump connector
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

A chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Claims

1. An apparatus comprising:

a frame;

a membrane coupled to the frame and configured to adhere to a surface of a semiconductor wafer, wherein the frame is configured to stretch the membrane in at least one lateral direction while the semiconductor wafer is adhered thereto.

2. The apparatus of claim 1, wherein the frame includes a plurality of frame members wherein in at least two of the plurality of frame members are configured to be displaced laterally away from each other to stretch the membrane in the at least one lateral direction.

3. The apparatus of claim 1, wherein the membrane comprises an elastic film.

4. The apparatus of claim 1, wherein the membrane is formed of a material comprising polyethylene.

5. The apparatus of claim 1, wherein the membrane comprises a flexible resin material.

6. The apparatus of claim 1, further comprising an adhesive layer disposed on a surface of the membrane.

7. The apparatus of claim 6, wherein the adhesive layer comprises a pressure-sensitive adhesive.

8. The apparatus of claim 6, wherein the adhesive layer comprises an ultraviolet-releasable adhesive.