Level shift circuit and shift register and display device

• US 20060197554A1
• Filed: 03/02/2006
• Published: 09/07/2006
• Est. Priority Date: 03/02/2005
• Status: Active Grant

• Current Assignee: Japan Display Incorporated
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Jinta, Seiichiro
• Granted Patent: US 7,663,593 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals

Abstract

A level shift circuit, a shift register, and a display device in which circuit operation is resistant to influence of variations in characteristics of elements such as transistors. The level shift circuit, includes a first switch turning on or off in accordance with a voltage of a first node, switching ON and OFF when the voltage is a first threshold value, and outputting a first voltage when ON state; a second switch turning on or off in accordance with the voltage of a second node, switching ON and OFF when the voltage is a second threshold value, and outputting a second voltage when ON state; a first capacitor receiving a first input signal at one terminal and connected at the other terminal to the first node; a second capacitor receiving a second input signal at one terminal, and connected at the other terminal to the second node; and a circuit for setting the voltage of the first node at the first threshold value and setting the voltage of the second node at the second threshold value in a predetermined period and setting the first node and the second node in a floating state after the predetermined period.

Claims

1. A level shift circuit for shifting the level of an input signal and outputting the result, comprising:

a first switch turning on or off in accordance with a voltage of a first node, switching ON and OFF when the voltage is a first threshold value, and outputting a first voltage to an output terminal of the level shift signal at the time of the ON state;

a second switch turning on or off in accordance with the voltage of a second node, switching ON and OFF when the voltage is a second threshold value, and outputting a second voltage to the output terminal at the time of the ON state;

a first capacitor receiving a first input signal at one terminal and connected at the other terminal to the first node;

a second capacitor receiving a second input signal at one terminal, and connected at the other terminal to the second node; and

a voltage setting circuit for setting the voltage of the first node at the first threshold value and setting the voltage of the second node at the second threshold value in a predetermined period and setting the first node and the second node in a floating state after the predetermined period.

2. A level shift circuit as set forth in claim 1, wherein

the first threshold value and the second threshold value are included within a range from the first voltage to the second voltage,

the first switch turns on when the voltage of the first node is at the second voltage side with respect to the first threshold value and turns off when it is at the first voltage side,

the second switch turns on when the voltage of the second node is at the first voltage side with respect to the second threshold value and turns off when it is at the second voltage side, and

the voltage setting circuit charges the first capacitor so that the voltage of the first node is at the second voltage side with respect to the first threshold value in a first period, supplies the voltage output from the first switch in the ON state to the first node in a second period after the charging, charges the second capacitor so that the voltage of the second node is at the first voltage side with respect to the second threshold value in a third period, and supplies the voltage output from the second switch in the ON state to the second node in a fourth period after the charging.

3. A level shift circuit as set forth in claim 2, wherein the voltage setting circuit charges the second capacitor in the third period after the first switch turns off in the second period.

4. A level shift circuit as set forth in claim 3, wherein the voltage setting circuit charges the second capacitor so that the voltage of the second node is at the second voltage side with respect to the second threshold value in the first period.

5. A level shift circuit as set forth in claim 3, wherein said voltage setting circuit includes:

a first voltage supply circuit supplying a predetermined voltage at said second voltage side with respect to said first threshold value to said first node in said first period,

a third switch connecting one terminal of said first switch from which said first voltage is output when on and said first node in said second period,

a second voltage supply circuit supplying a predetermined voltage at said first voltage side with respect to said second threshold value to said second node in said third period, and

a fourth switch connecting one terminal of said second switch from which said second voltage is output when on and said second node in said fourth period.

6. A level shift circuit as set forth in claim 5, wherein said first voltage supply circuit supplies a predetermined voltage at said second voltage side with respect to said first threshold value to said first node and said second node in said first period.

7. A level shift circuit as set forth in claim 3, wherein the voltage setting circuit disconnects the first switch and the output terminal and/or disconnects the second switch and the output terminal in the first period, the second period, the third period, and the fourth period.

8. A level shift circuit as set forth in claim 3, wherein the voltage setting circuit disconnects the first switch and the output terminal and connects the second switch and the output terminal in the first period and the second period and connects the first switch and the output terminal and disconnects the second switch and the output terminal in the third period and the fourth period.

9. A level shift circuit as set forth in claim 8, wherein

said first input signal and said second input signal have voltages from a third voltage to a fourth voltage,

when said first input signal changes from said third voltage to said fourth voltage, the voltage of said first node changes from said first threshold value to a direction toward said second voltage,

when said second input signal changes from said third voltage to said fourth voltage, the voltage of said second node changes from said second threshold value to a direction toward said second voltage, and

said voltage setting circuit supplies voltage to said first node in said first period and said second period when said first input signal has said third voltage and supplies voltage to said second node in said third period and said fourth period when said second input signal has said fourth voltage.

10. A level shift circuit as set forth in claim 7, wherein said voltage setting circuit includes:

a first voltage supply circuit supplying a predetermined voltage at said second voltage side with respect to said first threshold value to said first node in said first period,

a third switch connecting one terminal of said first switch from which said first voltage is output when on and said first node in said second period,

a second voltage supply circuit supplying a predetermined voltage at said first voltage side with respect to said second threshold value to said second node in said third period,

a fourth switch connecting one terminal of said second switch from which said second voltage is output when on and said second node in said fourth period, and

a fifth switch disconnecting the first switch and the output terminal and/or disconnecting the second switch and the output terminal in the first period, the second period, the third period, and the fourth period.

11. A level shift circuit as set forth in claim 8, wherein said voltage setting circuit includes:

a first voltage supply circuit supplying a predetermined voltage at said second voltage side with respect to said first threshold value to said first node in said first period,

a third switch connecting one terminal of said first switch from which said first voltage is output when on and said first node in said second period,

a second voltage supply circuit supplying a predetermined voltage at said first voltage side with respect to said second threshold value to said second node in said third period,

a fourth switch connecting one terminal of said second switch from which said second voltage is output when on and said second node in said fourth period, and

a fifth switch disconnecting the first switch and the output terminal and connecting the second switch and the output terminal in the first period and the second period and connecting the first switch and the output terminal and disconnecting the second switch and the output terminal in the third period and the fourth period.

12. A level shift circuit as set forth in claim 2, wherein the voltage setting circuit disconnects the first switch and the output terminal and/or disconnects the second switch and the output terminal in a fifth period in which at least a portion of the first period and the second period and at least a portion of the third period and the fourth period overlap.

13. A level shift circuit as set forth in claim 12, wherein the voltage setting circuit charges the second capacitor in the third period parallel to the charging of the first capacitor in the first period and supplies voltage to the second node in the fourth period parallel to the supply of voltage to the first node in the second period.

14. A level shift circuit as set forth in claim 12, wherein said voltage setting circuit includes:

a first voltage supply circuit supplying a predetermined voltage at said second voltage side with respect to said first threshold value to said first node in said first period,

a third switch connecting one terminal of said first switch from which said first voltage is output when on and said first node in said second period,

a second voltage supply circuit supplying a predetermined voltage at said first voltage side with respect to said second threshold value to said second node in said third period,

a fourth switch connecting one terminal of said second switch from which said second voltage is output when on and said second node in said fourth period, and

a fifth switch disconnecting the first switch and the output terminal and/or disconnecting the second switch and the output terminal in a fifth period.

15. A level shift circuit as set forth in claim 2, wherein said voltage setting circuit includes:

a first voltage supply circuit supplying a predetermined voltage at said second voltage side with respect to said first threshold value to said first node in said first period,

a third switch connecting one terminal of said first switch from which said first voltage is output when on and said first node in said first period and said second period,

a second voltage supply circuit supplying a predetermined voltage at said first voltage side with respect to said second threshold value to said second node in said third period,

a fourth switch connecting one terminal of said second switch from which said second voltage is output when on and said second node in said third period and said fourth period, and

a fifth switch disconnecting the first switch and the output terminal in said first period and said second period and disconnecting the second switch and the output terminal in said third period and said fourth period.

16. A level shift circuit as set forth in claim 2, wherein

said voltage setting circuit includes:

a first voltage supply circuit supplying a predetermined voltage at said second voltage side with respect to said first threshold value to said first node in said first period,

a third switch connecting one terminal of said first switch from which said first voltage is output when on and said first node in said second period,

a second voltage supply circuit supplying a predetermined voltage at said first voltage side with respect to said second threshold value to said second node in said third period, and

a fourth switch connecting one terminal of said second switch from which said second voltage is output when on and said second node in said fourth period;

said third switch includes

a first switch element having a first terminal connected to said first switch, a second terminal connected to said first node, and a control terminal inputting a voltage for controlling a conduction state between said first terminal and said second terminal,

a first capacitance element connected between said control terminal and first terminal of the first switch element,

a first drive input node inputting a voltage for driving said first switch element on or off, and

a second switch element connected between said first drive input node and said control terminal of the first switch element, turning on when the voltage of said control terminal of the first switch element is at said second voltage side with respect to a predetermined threshold voltage between said first voltage and said second voltage in a state where voltage for driving said first switch element on is input to said first drive input node, and turning off when at said first voltage side with respect to the predetermined threshold voltage; and

said fourth switch includes

a third switch element having a first terminal connected to said second switch, a second terminal connected to said second node, and a control terminal inputting a voltage for controlling a conduction state between said first terminal and said second terminal,

a second capacitance element connected between said control terminal and first terminal of the third switch element,

a second drive input node inputting a voltage for driving said third switch element on or off, and

a fourth switch element connected between said second drive input node and said control terminal of the third switch element, turning on when the voltage of said control terminal of the third switch element is at said first voltage side with respect to a predetermined threshold voltage between said first voltage and said second voltage in a state where voltage for driving said third switch element on is input to said second drive input node, and turning off when at said second voltage side with respect to the predetermined threshold voltage.

17. A level shift circuit as set forth in claim 16, wherein

said first switch element and said second switch element include insulated gate type transistors having first conductivity types,

said third switch element and said fourth switch element include insulated gate type transistors having second conductivity types,

said first capacitance element includes a parasitic capacitance element between a gate and drain of said insulated gate type transistor of said first switch element, and

said second capacitance element includes a parasitic capacitance element between a gate and drain of said insulated gate type transistor of said third switch element.

18. A level shift circuit as set forth in claim 2, further comprising:

a first input circuit inputting an input signal having a voltage from a third voltage to a fourth voltage as said first input signal and said second input signal to said first capacitor and said second capacitor in a period outputting a level shift signal from said output terminal and

a second input circuit inputting a predetermined voltage included in a range from said third voltage to said fourth voltage as said first input signal and said second input signal to said first capacitor and said second capacitor in a period where said voltage setting circuit sets voltages of said first node and said second node.

19. A level shift circuit as set forth in claim 18, wherein

said second input circuit inputs said third voltage to said first capacitor and said second capacitor as said predetermined voltage,

said voltage setting circuit sets the voltage of said second node to a sixth voltage shifted to said first voltage side from said second threshold value by exactly the difference between said third voltage and said fourth voltage in a sixth period after setting the voltage of said second node to said second threshold value, and

the voltages of said first node and said second node shift to said second voltage side by exactly said difference when the input signal from said first input circuit changes from said third voltage to said fourth voltage.

20. A level shift circuit as set forth in claim 19, wherein said voltage setting circuit includes

a third capacitor having one terminal connected to said second node and

a third voltage supply circuit supplying said fourth voltage to the other terminal of said third capacitor in said third period and said fourth period and supplying said third voltage to the other terminal of said third capacitor in said sixth period.

21. A shift register having a plurality of cascade-connected shift stages for successively transmitting pulse signals input to an initial stage to latter stages, wherein,

each shift stage has

a detection circuit for detecting a period during which the pulse signal is input from a former stage and a period during which the pulse signal is output to a next stage,

a level shift circuit for shifting the level of the pulse signal included in one cycle of the input clock signal and outputting the result in an input period and an output period of the pulse signal detected by the detection circuit;

and

an output circuit for outputting the signal output from the level shift circuit to the next stage as the pulse signal in the input period and the output period of the pulse signal detected by the detection circuit and outputting a signal of a constant level to the next stage in a predetermined period for initializing the level shift circuit;

the level shift circuit has

a first switch which turns on when the voltage of the first node is at a second voltage side with respect to a first threshold value included within a range from the first voltage to the second voltage, turns off when the voltage of the first node is at the first voltage side with respect to the first threshold value, and outputs the first voltage to the output terminal of the level shift signal at the time of the ON state,

a second switch which turns ON when the voltage of the second node is at the first voltage side with respect to the second threshold value included within the range from the first voltage to the second voltage, turns OFF when the voltage of the second node is at the second voltage side with respect to the second threshold value, and outputs the second voltage to the output terminal at the time of the ON state,

a first capacitor receiving as input the clock signal at one terminal and connected at the other terminal to the first node,

a second capacitor receiving as input the clock signal at one terminal and connected at the other terminal to the second node,

a voltage setting circuit for setting the voltage of the first node at the first threshold value and setting the voltage of the second node at the second threshold value in a predetermined period and setting the first node and the second node in a floating state after the predetermined period,

a first input circuit for inputting the clock signal to the first capacitor and the second capacitor in the input period and the output period of the pulse signal detected by the detection circuit, and

a second input circuit for inputting a predetermined voltage included in a range from a third voltage to a fourth voltage to the first capacitor and the second capacitor in place of the clock signal in a period during which the voltage setting circuit sets the voltage of the first node and the second node;

the clock signal is a signal alternately repeating the third voltage and the fourth voltage; and

two cascade-connected shift stages receive as input clock signals having equal cycles with each other but having different phases from each other.

22. A shift register as set forth in claim 21, wherein

two cascade-connected shift stages receive as input clock signals inverted in phase, and

the detection circuit included in each shift shaft detects a period during which said clock signal having the fourth voltage is shifted in level at said level shift circuit as an output period of a pulse signal.

23. A shift register as set forth in claim 21, wherein

one of two cascade-connected shift stages receives as input a first clock signal and the other receives as input a second clock signal,

a detection circuit included in one of two shift stages separated by another shift stage detects a period during which said clock signal having the third voltage is shifted in level in said level shift circuit as an output period of a pulse signal,

a detection circuit included in the other of said separated two shift stages detects a period during which said clock signal having the fourth voltage is shifted in level in said level shift circuit as an output period of a pulse signal,

a detection circuit included in the shift stage receiving as input said first clock signal and a detection circuit included at at stage after said shift stage detect a period during which clock signals having the same voltage are shifted in level in said level shift circuit as an output period of a pulse signal, and

said first clock signal changes from said third voltage to said fourth voltage when said second clock signal is said third voltage.

24. A shift register as set forth in claim 23, further comprising a pulse output circuit outputting one pulse signal corresponding to two cascade-connected shift stages when said two shift stages both output pulse signals.

25. A shift register as set forth in claim 21, wherein said level shift circuit has a sixth switch inserted in a route for inputting said first voltage to said first switch and/or a route for inputting said second voltage to said first switch, turning on at least in an input period and output period of a pulse signal detected by said detection circuit and said predetermined period, and turning off in other periods.

26. A display device comprising:

a level shift circuit for shifting the level of an input signal and outputting the result;

a pixel array including a plurality of pixels; and

a drive circuit for driving pixels of the pixel array in response to the level shift signal output from the level shift circuit, wherein

the level shift circuit has

a first switch turning on or off in accordance with a voltage of a first node, switching ON and OFF when the voltage is a first threshold value, and outputting a first voltage to an output terminal of the level shift signal at the time of the ON state;

a second switch turning on or off in accordance with the voltage of a second node, switching ON and OFF when the voltage is a second threshold value, and outputting a second voltage to the output terminal at the time of the ON state;

a first capacitor receiving as input a first input signal at one terminal and connected at the other terminal to the first node;

a second capacitor receiving as input a second input signal at one terminal, and connected at the other terminal to the second node; and

a voltage setting circuit for setting the voltage of the first node at the first threshold value and setting the voltage of the second node at the second threshold value in a predetermined period and setting the first node and the second node in a floating state after the predetermined period.

27. A display device comprising:

a pixel array including a plurality of pixels arranged in a matrix; and

a drive circuit having a first shift register for generating pulse signals for successively selecting rows of the pixel array and a second shift register for generating pulse signals for successively selecting pixels belonging to the selected row and driving a selected pixel, wherein

each of the first shift register and second shift register is provided with a plurality of cascade-connected shift stages for successively transmitting pulse signals input to an initial stage to latter stages,

each shift stage having

a detection circuit for detecting a period during which the pulse signal is input from a former stage and a period during which the pulse signal is output to a next stage,

a level shift circuit for shifting the level of the pulse signal included in one cycle of the input clock signal and outputting the result in an input period and an output period of the pulse signal detected by the detection circuit, and

an output circuit for outputting the signal output from the level shift circuit to the next stage as the pulse signal in the input period and the output period of the pulse signal detected by the detection circuit and outputting a signal of a constant level to the next stage in a predetermined period for initializing the level shift circuit;

the level shift circuit having

a first switch which turns on when the voltage of the first node is at a second voltage side with respect to a first threshold value included within a range from the first voltage to the second voltage, turns off when the voltage of the first node is at the first voltage side with respect to the first threshold value, and outputs the first voltage to the output terminal of the level shift signal at the time of the ON state,

a second switch which turns ON when the voltage of the second node is at the first voltage side with respect to the second threshold value included within the range from the first voltage to the second voltage, turns OFF when the voltage of the second node is at the second voltage side with respect to the second threshold value, and outputs the second voltage to the output terminal at the time of the ON state,

a first capacitor receiving as input the clock signal at one terminal and connected at the other terminal to the first node, a second capacitor receiving as input the clock signal at one terminal and connected at the other terminal to the second node,

a voltage setting circuit for setting the voltage of the first node at the first threshold value and setting the voltage of the second node at the second threshold value in a predetermined period and setting the first node and the second node in a floating state after the predetermined period,

a first input circuit for inputting the clock signal to the first capacitor and the second capacitor in the input period and the output period of the pulse signal detected by the detection circuit, and

a second input circuit for inputting a predetermined voltage included in a range from a third voltage to a fourth voltage to the first capacitor and the second capacitor in place of the clock signal in a period during which the voltage setting circuit sets the voltage of the first node and the second node;

the clock signal being a signal alternately repeating the third voltage and the fourth voltage; and

two cascade-connected shift stages receiving as input clock signals having equal cycles with each other but having different phases from each other.