Measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications

• US 20060197607A1
• Filed: 02/22/2005
• Published: 09/07/2006
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Castro, Rafael
• Granted Patent: US 7,325,171 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: G05B 19/042 using digital processors G05B19/05 takes precedence
• CPC Class Codes: G05B 2219/25041 Select between several clock signals
• CPC Class Codes: G05B 2219/25399 Variable, settable clock or cycle, phase duration

Abstract

A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Claims

1. A system for implementing control loop operations, the system comprising:

a plurality of subsystems, wherein at least a portion of the plurality of subsystems are operable to provide a plurality of timing signals for the system; and

a real-time monitoring unit coupled to the portion of the plurality of subsystems, wherein the real-time monitoring unit is operable to receive the plurality of timing signals and to select a control loop timing signal out of the plurality of timing signals, wherein the real-time monitoring unit comprises;

a first edge detector unit operable to receive the control loop timing signal and detect a significant event in the control loop timing signal indicating a start of a time period allotted for completion of the control loop operation, wherein the real-time monitoring unit is operable to determine whether the control loop operation is performed within the time period.

2. The system of claim 1, further comprising a processing unit coupled to the plurality of subsystems and to the real-time monitoring unit, wherein the processing unit is operable to program the real-time monitoring unit to select the control loop timing signal received from the one of the plurality of subsystems.

3. The system of claim 2, wherein the processing unit is operable to program the plurality of subsystems to perform the control loop operation.

4. The system of claim 2, wherein the first edge detector unit is operable to assert an event active (EA) bit in response to detection of the significant event in the control loop timing signal.

5. The system of claim 4, wherein the processing unit is operable to start the control loop operation when the EA bit is asserted.

6. The system of claim 5, wherein the real-time monitoring unit is operable to notify to the processing unit when the EA bit is asserted, wherein the processing unit is operable to start the control loop operation in response to receiving the notification.

7. The system of claim 4, wherein, after the EA bit is asserted, one of the plurality of subsystems is operable to provide an interrupt to the processing unit, wherein the processing unit is operable to start the control loop operation in response to receiving the interrupt.

8. The system of claim 5, wherein the processing unit is operable to provide an acknowledge signal to the real-time monitoring unit when the control loop operation has been completed.

9. The system of claim 8, wherein the real-time monitoring unit is operable to deassert the EA bit in response to receiving the acknowledge signal from the processing unit.

10. The system of claim 8, wherein the acknowledge signal is received by the real-time monitoring unit before a subsequent significant event is detected if the control loop operation was performed within the allotted time period.

11. The system of claim 8, further comprising a second edge detector unit operable to detect an error in the implementation of the control loop operation.

12. The system of claim 11, wherein if the acknowledge signal is received by the real-time monitoring unit after a subsequent significant event is detected, the second edge detector unit is operable to assert a latency error bit to indicate the control loop operation was not completed within the allotted time period.

13. The system of claim 12, wherein the real-time monitoring unit is operable to notify the processing unit when the latency error bit is asserted to indicate that the control loop operation was not performed within the allotted time period.

14. The system of claim 13, wherein the processing unit is operable to shut down the system in response to receiving the notification that the latency error bit is asserted.

15. A data acquisition system for implementing control loop operations, the data acquisition system comprising:

a plurality of subsystems, wherein at least a portion of the plurality of subsystems are operable to provide a plurality of timing signals for the data acquisition system; and

a data acquisition device coupled to the plurality of subsystems, the data acquisition device comprising;

a real-time monitoring unit operable to receive the plurality of timing signals and to select a control loop timing signal out of the plurality of timing signals, wherein the real-time monitoring unit comprises;

a first edge detector unit operable to receive the control loop timing signal and detect a significant event in the control loop timing signal indicating a start of a time period allotted for completion of the control loop operation, wherein the real-time monitoring unit is operable to determine whether the control loop operation is performed within the time period.

16. The data acquisition system of claim 15, further comprising a processing unit coupled to the plurality of subsystems and to the real-time monitoring circuit, wherein the processing unit is operable to program the real-time monitoring unit to select the control loop timing signal received from the one of the plurality of subsystems.

17. The data acquisition system of claim 16, wherein the first edge detector unit is operable to assert an event active (EA) bit in response to detection of the significant event in the control loop timing signal, wherein the real-time monitoring unit is operable to notify to the processing unit when the EA bit is asserted, wherein the processing unit is operable to start the control loop operation in response to receiving the notification.

18. The data acquisition system of claim 17, wherein the processing unit is operable to provide an acknowledge signal to the real-time monitoring unit when the control loop operation has been completed, wherein the real-time monitoring unit is operable to deassert the EA bit in response to receiving the acknowledge signal from the processing unit.

19. The data acquisition system of claim 18, further comprising a second edge detector unit operable to detect an error in the implementation of the control loop operation.

20. The data acquisition system of claim 19, wherein if the acknowledge signal is received by the real-time monitoring unit after a subsequent significant event is detected, the second edge detector unit is operable to assert a latency error bit to indicate the control loop operation was not completed within the allotted time period, wherein the real-time monitoring unit is operable to notify the processing unit when the latency error bit is asserted.

21. The data acquisition system of claim 15, further comprising a unit under test (UUT), wherein the UUT comprises a sensor operable to provide the data acquisition device with sensor data, wherein the data acquisition device is operable to provide the sensor data to the processing unit for analysis during the control loop operation.

22. A method for implementing control loop operations in a system, wherein the system comprises a plurality of subsystems and a real-time monitoring unit, the method comprising:

the plurality of subsystems providing a plurality of timing signals to the system;

a real-time monitoring unit receiving the plurality of timing signals from the plurality of subsystems and selecting a control loop timing signal out of the plurality of timing signals;

detecting a significant event in the control loop timing signal indicating a start of a time period allotted for completion of the control loop operation; and

the real-time monitoring unit determining whether the control loop operation is performed within the time period.

23. The method of claim 22, wherein the system further comprises a processing unit, wherein said selecting the control loop timing signal out of the plurality of timing signals comprises the processing unit programming the real-time monitoring unit to select the control loop timing signal received from the one of the plurality of subsystems.

24. The method of claim 23, further comprising the processing unit programming the plurality of subsystems to perform the control loop operation.

25. The method of claim 23, wherein the real-time processing unit comprises a first edge detector unit for detecting the significant event in the control loop timing signal indicating the start of the time period allotted for the completion of the control loop operation, further comprising the first edge detector unit asserting an event active (EA) bit in response to detection of the significant event in the control loop timing signal.

26. The method of claim 25, further comprising the processing unit starting the control loop operation when the EA bit is asserted.

27. The method of claim 25, further comprising the real-time monitoring unit notifying the processing unit when the EA bit is asserted and the processing unit starting the control loop operation in response to receiving the notification.

28. The method of claim 27, further comprising the processing unit providing an acknowledge signal to the real-time monitoring unit when the control loop operation has been completed.

29. The method of claim 28, further comprising the real-time monitoring unit deasserting the EA bit in response to receiving the acknowledge signal from the processing unit.

30. The method of claim 28, wherein the real-time monitoring unit comprises a second edge detector unit for detecting an error in the implementation of the control loop operation.

31. The method of claim 30, wherein said determining whether the control loop operation is performed within the time period comprises asserting a latency error bit to indicate the control loop operation was not completed within the allotted time period if the acknowledge signal is received by the real-time monitoring unit after a subsequent significant event is detected.

32. The method of claim 31, further comprising the real-time monitoring unit notifying the processing unit when the latency error bit is asserted to indicate that the control loop operation was not performed within the allotted time period.

33. The method of claim 32, further comprising the processing unit shutting down the system in response to receiving the notification that the latency error bit is asserted.