CMOS image sensor with a low-power architecture
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Abstract
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.
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Citations
43 Claims
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1-32. -32. (canceled)
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33. An image sensor, comprising:
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an array of photosensitive pixels arranged into rows and columns;
means for reading out analog pixel values from the columns of the array;
a first analog-to-digital converter, the first analog-to-digital converter converting, at a first timing, analog pixel values from first colored pixels in the array; and
a second analog-to-digital converter, the second analog-to-digital converter converting, at a second timing offset from the first timing, analog pixel values from other colored pixels in the array, wherein said second timing is about 50 percent of the way through a conversion cycle represented by said first timing. - View Dependent Claims (34, 35, 36)
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37. An image sensor, comprising:
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an array of photosensitive pixels arranged into rows and columns; and
column readout circuitry connected to the columns, the circuitry producing a plurality of bias electrical values to be used during acquisition of image signals from the columns and turning off said bias electrical signals at times during the acquisition when the biases are not needed, wherein the bias signals include a clamped signal. - View Dependent Claims (38, 39, 40, 41, 42, 43)
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Specification