Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays

• US 20060198189A1
• Filed: 01/03/2006
• Published: 09/07/2006
• Est. Priority Date: 01/03/2005
• Status: Abandoned Application

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting, Lai, Sheng-Chih
• Application Number:
  US11/324,495
• Publication Number:
  US 20060198189A1
• Time in Patent Office: Days
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

Claims

1. A memory cell comprising:

a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region;

a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;

a charge storage layer disposed above the tunnel dielectric structure;

an insulating layer disposed above the charge storage layer; and

a gate electrode disposed above the insulating layer, wherein the gate electrode comprises a material having a work function value greater than that of N⁺ polysilicon.

2. The memory cell according to claim 1, wherein the gate electrode comprises platinum.

3. The memory cell according to claim 1, wherein the tunnel dielectric structure comprises at least two dielectric layers each having a thickness of up to about 4 nm.

4. The memory cell according to claim 1, wherein the tunnel dielectric structure comprises a first silicon oxide layer, a first silicon nitride layer above the first silicon oxide layer, and a second silicon oxide layer above the first silicon nitride layer.

5. The memory cell according to claim 1, wherein the charge storage layer comprises at least one material selected from the group consisting of silicon nitride, Al₂O₃, and HfO₂.

6. The memory cell according to claim 1, wherein the insulating layer comprises silicon oxide.

7. The memory cell according to claim 1, wherein the tunnel dielectric structure has a negligible trapping efficiency.

8. A memory array comprising a plurality of memory cells according to claim 1.

9. The memory array according to claim 8, wherein at least two of the plurality of memory cells are separated from each other by at least one of a shallow-trench isolation and a silicon-on-insulator isolation.

10. The memory array according to claim 8, wherein the memory array comprises at least two word lines, at least two bit lines, and at least one source line.

11. The memory array according to claim 8, wherein the memory array comprises at least one bit line selecting transistor coupled to a corresponding bit line.

12. The memory array according to claim 8, wherein the memory array comprises at least one source line selecting transistor coupled to a corresponding source line.

13. The memory array according to claim 8, wherein the substrate comprises at least a pair of shallow junctions for the memory device.