Semiconductor device and manufacturing method

• US 20060199319A1
• Filed: 12/12/2003
• Published: 09/07/2006
• Est. Priority Date: 01/28/2003
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Takaishi, Masaru
• Granted Patent: US 7,288,815 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different from the first conductivity type, the source region (25) being formed at a rim of a trench (17) having a depth sufficient to penetrate through the channel region (4); a drain region (2) of the second conductivity type formed at a region adjacent to a bottom of the trench (17); a gate insulating film (13) formed along an inner side wall of the trench (17); a gate electrode (26, 36) arranged in the trench (17) so as to be opposed to the channel region (4) with the gate insulating film (13) interposed therebetween; a conductive layer (37, 40, 40a, 40b) formed in the trench (17) so as to be nearer to the drain region (2) than the gate electrode (26, 36); and an insulating layer (15) surrounding the conductive layer (37, 40, 40a, 40b) to electrically insulate the conductive layer (37, 40, 40a, 40b) from the gate electrode (26, 36) and the drain region (2).

Claims

1. A semiconductor device, comprising:

a channel region of a first conductivity type formed at a surface layer portion of a semiconductor substrate;

a source region of a second conductivity type which is different from the first conductivity type, the source region being formed at a rim of a trench having a depth sufficient to penetrate through the channel region;

a drain region of the second conductivity type formed at a region adjacent to a bottom of the trench;

a gate insulating film formed along an inner side wall of the trench;

a gate electrode arranged in the trench so as to be opposed to the channel region with the gate insulating film interposed therebetween;

a conductive layer formed in the trench so as to be nearer to the drain region than the gate electrode; and

an insulating layer surrounding the conductive layer to electrically insulate the conductive layer from the gate electrode and the drain region.

2. A semiconductor device according to claim 1, wherein the conductive layer is made of polysilicon which is made conductive by introduction of an impurity.

3. A semiconductor device according to claim 1, comprising the plurality of conductive layers, wherein the insulating layer is arranged between the plurality of conductive layers.

4. A semiconductor device according to claims 1, wherein the inner side wall of the trench has a substantially flat face and the flat face is a face in the channel region, the face having a specific plane direction to give a low resistance when electric current flows along the face.

8. A semiconductor device according to claim 2, comprising the plurality of conductive layers, wherein the insulating layer is arranged between the plurality of conductive layers.

9. A semiconductor device according to claim 2, wherein the inner side wall of the trench has a substantially flat face and the flat face is a face in the channel region, the face having a specific plane direction to give a low resistance when electric current flows along the face.

10. A semiconductor device according to claim 3, wherein the inner side wall of the trench has a substantially flat face and the flat face is a face in the channel region, the face having a specific plane direction to give a low resistance when electric current flows along the face.

11. A semiconductor device according to claim 8, wherein the inner side wall of the trench has a substantially flat face and the flat face is a face in the channel region, the face having a specific plane direction to give a low resistance when electric current flows along the face.

5. A manufacturing method of a semiconductor device comprising:

a channel region of a first conductivity type formed at a surface layer portion of a semiconductor substrate;

a source region of a second conductivity type which is different from the first conductivity type, the source region being formed at a rim of a trench having a depth sufficient to penetrate through the channel region;

a drain region of the second conductivity type formed at a region adjacent to a bottom of the trench;

a gate insulating film formed along an inner side wall of the trench;

a gate electrode arranged in the trench so as to be opposed to the channel region with the gate insulating film interposed therebetween;

a conductive layer formed in the trench so as to be nearer to the drain region than the gate electrode; and

an insulating layer surrounding the conductive layer to electrically insulate the conductive layer from the gate electrode and the drain region, the method comprising;

a step of forming an epitaxial layer of the second conductivity type at a surface layer portion of a semiconductor substrate;

a step of forming the trench at the epitaxial layer;

a step of forming a first insulating layer at a bottom of the trench;

a step of forming the conductive layer on the first insulating layer in the trench after the step of forming the first insulating layer;

a step of forming a second insulating layer at an exposed surface of the conductive layer after the step of forming the conductive layer, the second insulating layer composing the insulating layer together with the first insulating layer;

a step of forming the gate insulating film along the inner side wall of the trench;

a step of forming the gate electrode in the trench, the gate electrode being electrically insulated from the conductive layer by the insulating layer;

a step of forming the channel region of the first conductivity type at the epitaxial layer, the channel region being to be opposed to the gate electrode with the gate insulating film interposed therebetween; and

a step of forming the source region of the second conductivity type at a region of the epitaxial layer corresponding to a rim of the trench.

6. A manufacturing method of a semiconductor device according to claim 5, wherein

the step of forming the first insulating layer includes a step of forming a sacrificial oxide film by performing thermal oxidation for an inner wall of the trench and a step of removing the sacrificial oxide film with a portion thereof existing at a bottom of the trench being left, and

the step of forming the second insulating layer includes a step of oxidizing an exposed surface of the conductive layer.

7. A manufacturing method of a semiconductor device according to claim 5, wherein the step of forming the gate electrode includes a step of forming a polysilicon film which is made conductive by introduction of an impurity.

12. A manufacturing method of a semiconductor device according to claim 6, wherein the step of forming the gate electrode includes a step of forming a polysilicon film which is made conductive by introduction of an impurity.