Method for fabricating capacitor in semiconductor device

• US 20060199329A1
• Filed: 12/27/2005
• Published: 09/07/2006
• Est. Priority Date: 03/03/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Sung-Kwon
• Granted Patent: US 7,687,344 B2
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug

Abstract

A first insulation layer is formed on a substrate structure including an inter-layer insulation layer and a storage node contact plug. The first insulation layer is etched to form a first opening exposing a portion of the storage node contact plug. The first opening is filled with an organic polymer layer. An etch stop layer and a second insulation layer are formed on the organic polymer layer and the first insulation layer. A photoresist pattern is formed on the second insulation layer. The second insulation layer and the etch stop layer are etched to form a second opening exposing a portion of the organic polymer layer. The photoresist pattern and the organic polymer layer are removed, thereby extending a portion of the second opening. A storage node is formed over the extended second opening and the second insulation layer.

Claims

1. A method for fabricating a capacitor in a semiconductor device, comprising:

forming a first insulation layer on a substrate structure that has an inter-layer insulation layer and a storage node contact plug;

etching the first insulation layer to form a first opening exposing a predetermined portion of the storage node contact plug;

filling the first opening with an organic polymer layer;

sequentially forming an etch stop layer and a second insulation layer on the organic polymer layer and the first insulation layer;

forming a photoresist pattern on the second insulation layer using a mask;

etching a predetermined portion of the second insulation layer and the etch stop layer to form a second opening exposing a predetermined portion of the organic polymer layer;

simultaneously removing the photoresist pattern and the organic polymer layer, thereby extending a portion of the second opening; and

forming a storage node over the extended second opening and the second insulation layer.

2. The method of claim 1, wherein the filling of the first opening comprises:

forming a layer of an organic polymer material over the first opening and the first insulation layer; and

planarizing the layer of the organic polymer material by one of an etch-back process and a chemical mechanical polishing (CMP) process.

3. The method of claim 1, further comprising forming the storage node contact plug using one selected from the group consisting of polysilicon, tungsten (W), tungsten nitride (WN), titanium nitride (TiN), and titanium tungsten (TiW).

6. The method of claim 1, further comprising forming the inter-layer insulation layer by including one selected from the group consisting of a high density plasma (HDP) layer, a tetraethyl orthosilicate (TEOS) layer, a boro-phospho-silicate glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a plasma enhanced chemical vapor deposition (PECVD) layer, a silicon oxynitride (SiON) layer, and a combination thereof.

7. The method of claim 1, wherein the forming of the second insulation layer comprises forming one of a single layer and multiple layers.

8. The method of claim 1, after the forming of the second insulation layer, further comprising forming a hard mask layer on the second insulation layer.

9. The method of claim 8, wherein the forming of the hard mask layer comprises including one selected from the group consisting of polysiliscon, SiON, W, amorphous carbon, black diamond, siloxane, silicon monoxide (SiO) polymer including silsesquioxane-type silicon (Si) element, and a combination thereof.

10. The method of claim 1, wherein the forming of the first insulation layer and the second insulation layer comprises including an oxide material.

11. The method of claim 1, wherein the forming of the etch stop layer comprises including one selected from the group consisting of a nitride material, SiON, tritantalum tetraoxide (Ta₃O₄), aluminum oxide (Al₂O₃), atomic layer deposition (ALD) nitride, and silicon boron nitride (SiBN).

12. The method of claim 1, wherein the forming of the photoresist pattern on the second insulation layer comprises using a mask that is arranged in zigzag pattern.

4. A method for fabricating a capacitor in a semiconductor device, comprising:

forming a first insulation layer on a substrate structure that has an inter-layer insulation layer and a storage node contact plug;

etching the first insulation layer to form a first opening exposing a predetermined portion of the storage node contact plug;

filling the first opening with a layer of amorphous carbon;

sequentially forming an etch stop layer and a second insulation layer on the amorphous carbon layer and the first insulation layer;

forming a photoresist pattern on the second insulation layer using a mask;

etching a predetermined portion of the second insulation layer and the etch stop layer to form a second opening exposing a predetermined portion of the amorphous carbon layer;

simultaneously removing the photoresist pattern and the amorphous carbon layer, thereby extending a portion of the second opening; and

forming a storage node over the extended second opening and the second insulation layer.

5. A method for fabricating a capacitor in a semiconductor device, comprising:

forming a first insulation layer on a substrate structure that has an inter-layer insulation layer and a storage node contact plug;

etching the first insulation layer to form a first opening exposing a predetermined portion of the storage node contact plug;

forming a layer of amorphous carbon material over the first opening and the first insulation layer;

planarizing the layer of amorphous carbon material by one of an etch-back process and a chemical mechanical polishing (CMP) process;

sequentially forming an etch stop layer and a second insulation layer on the amorphous carbon layer and the first insulation layer;

forming a photoresist pattern on the second insulation layer using a mask;

etching a predetermined portion of the second insulation layer and the etch stop layer to form a second opening exposing a predetermined portion of the amorphous carbon layer;

simultaneously removing the photoresist pattern and the amorphous carbon layer, thereby extending a portion of the second opening; and

forming a storage node over the extended second opening and the second insulation layer.