Integrated transceiver with envelope tracking

• US 20060199553A1
• Filed: 03/07/2005
• Published: 09/07/2006
• Est. Priority Date: 03/07/2005
• Status: Abandoned Application

• Current Assignee: Andrew LLC (CommScope Holding Company, Inc.)
• Original Assignee: Andrew Corporation (CommScope Holding Company, Inc.)
• Inventors: Kenington, Peter Blakeborough
• Application Number:
  US11/073,535
• Publication Number:
  US 20060199553A1
• Time in Patent Office: Days
• US Class Current: 455/127.1
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

A transceiver comprises an amplifying circuit for amplifying an input signal to produce an output signal. A power supply is operable for varying the level of power supplied to the amplifying circuit in response to variation of an input signal envelope directed to the power supply. A processing circuit is operable for digitally detecting the input signal envelope to provide variation of the power supply level. The processing circuit is further operable for digitally delaying the digital input signal envelope to time align the power supply level with the input signal.

Claims

1. A transceiver comprising:

an amplifying circuit for amplifying an input signal to produce an output signal;

a power supply operable for varying the level of power supplied to the amplifying circuit in response to variation of an input signal envelope directed to the power supply;

a processing circuit operable for digitally detecting the input signal envelope to provide variation of the power supply level;

the processing circuit further operable for digitally delaying the digital input signal envelope to time align the power supply level with the input signal.

2. The transceiver of claim 1 wherein the processing circuit is further operable for digitally delaying the input signal for further time alignment of the power supply level and input signal.

3. The transceiver of claim 1 wherein the processing circuit provides crest factor reduction that digitally detects the input signal envelope, the processing circuit being further operable for using the digitally detected envelope for varying the power supply level.

4. The transceiver of claim 1 wherein the processing circuit includes a predistortion circuit for predistorting the input signal, the predistortion circuit including an input signal path and a feedback signal path, and the processing circuit operable for digitally delaying a signal in at least one of the input and feedback signal paths.

5. The transceiver of claim 4 wherein the predistortion circuit is a digital predistortion circuit.

6. The transceiver of claim 4 wherein the predistortion circuit is adaptable, and the processing circuit includes circuitry for adapting the predistortion circuit based on a signal in at least one of the input and feedback signal paths.

7. The transceiver of claim 1 further comprising an envelope predistortion circuit operable for predistorting the input signal envelope before it is directed to the power supply for addressing envelope tracking capabilities of the power supply.

8. The transceiver of claim 7 wherein the processing circuit is further operable for digitally delaying the predistorted input signal envelope to time align the power supply level with the input signal.

9. A transceiver comprising:

an amplifying circuit for amplifying an input signal to produce an output signal;

a power supply operable for varying the level of power supplied to the amplifying circuit in response to variation of an input signal envelope directed to the power supply;

an envelope detection circuit operable for detecting the input signal envelope and directing the detected input signal envelope to the power supply;

a processing circuit operable for digitally delaying at least one of the input signal envelope and input signal respectively to time align the power supply level with the input signal.

10. The transceiver of claim 9 wherein the envelope detection circuit is further operable for digitally detecting the input signal envelope to provide variation of the power supply level.

11. The transceiver of claim 9 wherein the processing circuit includes a predistortion circuit for predistorting the input signal, the predistortion circuit including an input signal path and a feedback signal path, and the processing circuit operable for digitally delaying a signal in at least one of the input and feedback signal paths.

12. The transceiver of claim 9 wherein the predistortion circuit is a digital predistortion circuit.

13. The transceiver of claim 11 wherein the predistortion circuit is adaptable, and the processing circuit includes circuitry for adapting the predistortion circuit based on a signal in at least one of the input and feedback signal paths.

14. The transceiver of claim 9 further comprising an envelope predistortion circuit operable for predistorting the input signal envelope before it is directed to the power supply for addressing envelope tracking capabilities of the power supply.

15. The transceiver of claim 14 wherein the processing circuit is further operable for digitally delaying predistorted input signal envelope to time align the power supply level with the input signal.

16. A transceiver comprising:

an amplifying circuit for amplifying an input signal to produce an output signal;

a power supply operable for varying the level of power supplied to the amplifying circuit in response to variation of an input signal envelope directed to the power supply;

a processing circuit operable for digitally detecting the input signal envelope to provide variation of the power supply level;

the processing circuit including an envelope predistortion circuit operable for receiving and predistorting the input signal envelope before it is directed to the power supply.

17. The transceiver of claim 16 wherein the processing circuit is further operable for digitally delaying the digital input signal envelope to time align the power supply level with the input signal.

18. The transceiver of claim 16 wherein the envelope predistortion circuit includes an input signal path and a feedback signal path, the processing circuit operable for digitally delaying a signal in at least one of the input and feedback signal paths.

19. The transceiver of claim 16 wherein the envelope predistortion circuit is adaptable, the processing circuit further including circuitry for adapting the envelope predistortion circuit based on a signal in at least one of an input signal path and a feedback signal path.

20. The transceiver of claim 19 wherein the processing circuit is operable for digitally delaying a signal in at least one of the input and feedback signal paths.

21. The transceiver of claim 16 wherein the processing circuit includes a predistortion circuit for predistorting the input signal, the predistortion circuit including an input signal path and a feedback signal path, the processing circuit operable for digitally delaying a signal in at least one of the input and feedback signal paths.

22. The transceiver of claim 21 wherein the envelope predistortion circuit is adaptable, the processing circuit including circuitry for adapting the predistortion circuit based on a signal in at least one of the input and feedback signal paths.

23. A method of amplifying a signal comprising:

amplifying an input signal with an amplifier to produce an output signal;

digitally detecting an envelope of the input signal and varying the level of power supplied to the amplifier by the power supply in response to variation of the input signal envelope;

digitally delaying the digital input signal envelope to time align the power supply level with the input signal.

24. The method of claim 23 further comprising digitally delaying the input signal for further time alignment of the power supply level and input signal.

25. The method of claim 23 further comprising predistorting the input signal with a predistortion circuit including an input signal path and a feedback signal path and digitally delaying a signal in at least one of the input and feedback signal paths.

26. The method of claim 25 further comprising adapting the predistortion circuit based on a signal in at least one of the input and feedback paths.

27. The method of claim 23 further comprising predistorting the input signal envelope before it is directed to the power supply.

33. The method of claim 23 further comprising digitally delaying the predistorted input signal envelope to time align the power supply level with the input signal.

28. A method of amplifying a signal comprising:

amplifying an input signal with an amplifier to produce an output signal;

detecting an envelope of the input signal and varying the level of power supplied to the amplifier by the power supply in response to variation of the input signal envelope;

digitally delaying at least one of the input signal envelope and input signal respectively to time align the power supply level with the input signal.

29. The method of claim 28 further comprising digitally detecting the input signal envelope to provide variation of the power supply level.

30. The method of claim 28 further comprising predistorting the input signal with a predistortion circuit including an input signal path and a feedback signal path and digitally delaying a signal in at least one of the input and feedback signal paths.

31. The method of claim 28 further comprising adapting the predistortion circuit based on a signal in at least one of the input and feedback paths.

32. The method of claim 28 further comprising predistorting the input signal envelope before it is directed to the power supply.

34. A method of amplifying a signal comprising:

amplifying an input signal with an amplifier to produce an output signal;

digitally detecting an envelope of the input signal and varying the level of power supplied to the amplifier by the power supply in response to variation of the input signal envelope;

predistorting the input signal envelope with an envelope predistortion circuit before it is directed to the power supply.

35. The method of claim 34 further comprising digitally delaying the digital input signal envelope to time align the power supply level with the input signal.

36. The method of claim 34 wherein the envelope predistortion circuit includes an input signal path and a feedback signal path, and further comprising digitally delaying a signal in at least one of the input and feedback signal paths.

37. The method of claim 34 further comprising adapting the envelope predistortion circuit based on a signal in at least one of an input signal path and a feedback signal path.

38. The method of claim 37 wherein the processing circuit is operable for digitally delaying a signal in at least one of the input and feedback signal paths.

39. The method of claim 34 further comprising predistorting the input signal with a predistortion circuit including an input signal path and a feedback signal path and digitally delaying a signal in at least one of the input and feedback signal paths.

40. The method of claim 39 further comprising adapting the predistortion circuit based on a signal in at least one of the input and feedback signal paths.