Microprocessor system for a machine controller in safety-certifiable applications

• US 20060200257A1
• Filed: 02/24/2006
• Published: 09/07/2006
• Est. Priority Date: 03/03/2005
• Status: Abandoned Application

• Current Assignee: WAGO Verwaltungsgesellschaft mbH (WAGO Holding GmbH)
• Original Assignee: WAGO Verwaltungsgesellschaft mbH (WAGO Holding GmbH)
• Inventors: Kirste, Hans-Herbert, Lehzen, Michael
• Application Number:
  US11/361,046
• Publication Number:
  US 20060200257A1
• Time in Patent Office: Days
• US Class Current: 700/79
• CPC Class Codes: G05B 19/0428 Safety, monitoring G05B19/0423 takes precedence
• CPC Class Codes: G05B 2219/2227 Common memory as well as local memory
• CPC Class Codes: G05B 2219/24008 Safety integrity level, safety integrated systems SIL SIS
• CPC Class Codes: G05B 2219/25341 Single chip programmable controller

Abstract

A microprocessor system for a machine controller used in safety-critical applications includes a main processor, a program and/or data store, an input/output unit and a bus. The bus couples the components and at least one safety processor together. The safety processor has a dedicated program/data store. A safe transmission link is provided for loading programs and data into the safety processor. The transmission link includes the general bus and a mailbox (87) which has a state machine whose input is connected to the general bus and whose output is connected to the safety processor. As a result, program data can be written to the safety processor'"'"'s program store without the risk of being manipulated. This makes it possible for the program data to be loaded into the safety processor safely using the bus which is not safe per se. The bus thus does not need to belong to the safe area. Certification of the microprocessor controller is thus simplified.

Claims

1. A microprocessor system for a machine controller in safety-certifiable applications, said microprocessor system comprising:

an unsafe area having a main processor;

a program and data store;

an input/output unit;

a bus for coupling the main processor the data store and the input/output unit;

a safe area having at least one safety processor which has a dedicated program/data store, said at least one safety processor and said dedicated program/data store being connected to the bus, wherein a protected transmission channel is designed to store programs and data in the dedicated program/data store of the at least one safety processor;

a data source which can be connected to the bus and has a checking data area and a mailbox associated with the at least one safety processor, wherein an whose input is connected to the bus and an output is connected to the dedicated program/data store of the at least one safety processor; and

a state machine which is designed to control data transmission from the data source to the dedicated program/data store of the at least one safety processor and is designed to use data from the checking data area for the purpose of verification.

2. The microprocessor system as claimed in claim 1, further comprising a second safety processor.

3. The microprocessor system as claimed in claim 2, wherein the at least one safety processor and the second safety processor are connected in parallel to the mailbox.

4. The microprocessor system as claimed in claim 2, further comprising a dedicated mailbox for the dedicated connection of the second safety processor.

5. The microprocessor system as claimed in claim 2 further comprising an additional mailbox whose input is connected to the at least one safety processor and whose output is connected to the second safety processor.

6. The microprocessor system as claimed in claim 1 wherein the state machine is designed to check that identification features of the checking data area match those of the safety processors.

7. The microprocessor system as claimed in claim 1 wherein the safe transmission channel is capable of handling reverse signals.

8. The microprocessor system as claimed in claim 1 wherein the main processor and the at least one safety processor arranged on a die.

9. The microprocessor system as claimed in claim 8, wherein the data store, the input/output unit, the bus and the mailbox arranged on said die.

10. The microprocessor system as claimed in claim 1 wherein the safe area is physically isolated from the unsafe area.

11. The microprocessor system as claimed in claim 10 wherein said physical isolation is achieved using a depression in the die.

12. The microprocessor system as claimed in claim 3 further comprising an additional mailbox whose input is connected to the at least one safety processor and whose output is connected to the second safety processor.

13. The microprocessor system as claimed in claim 2 wherein the main processor, the at least one safety processor, and the second safety processor are arranged on a die.