Variable length command pull with contiguous sequential layout

• US 20060200595A1
• Filed: 03/02/2005
• Published: 09/07/2006
• Est. Priority Date: 03/02/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Maharana, Parag, Hallyal, Basavaraj, Thangaraj, Senthil Murugan, Anand, Gurpreet Singh
• Granted Patent: US 7,917,659 B2
• Time in Patent Office: Days
• US Class Current: 710/30
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) bus. In one embodiment, a device and method for reducing the load on the PCI Bus is described. In yet another embodiment, a device and method is described for constructing a variable length command block comprising message frames and aligning all message frames for a particular command block that are contiguous in memory.

Claims

1. A method of receiving a variable length command block at a peripheral from a PCI bus, the method comprising:

receiving a variable length command block, via the PCI bus, from at least one processor;

locating a first frame within the variable length command block;

identifying the total number of frames, within the variable length command block, from data integrated within the first frame;

reading the total number of frames within the variable length command block; and

determining the command within the variable length command block.

2. The method of claim 1, wherein the method is used in a dual addressing scheme.

3. The method of claim 1, wherein the message frames are aligned for a particular command block that is contiguously stored in memory.

4. The method of claim 1, wherein the data integrated within the first frame is a three bit word.

5. The method of claim 1, wherein the variable length command block is received by firmware associated with a memory device.

6. The method of claim 5, wherein the memory device is a redundant array of independent disks.

7. A device that receives a variable length command block from a PCI bus, the controller comprising:

a PCI bus interface that receives data from the PCI bus;

a peripheral interface that communicates data to a peripheral; and

a controller, coupled to the PCI bus interface and the peripheral interface, that receives a variable length command block and identifies the length of the variable length command block from data integrated in a frame within the variable length command block.

8. The device of claim 7, wherein the device is integrated into firmware associated with a peripherial.

9. The controller of claim 7, wherein the controller is able to identify the length of the variable length command block from data integrated in the first frame of the variable length command block.

10. The controller of claim 9, wherein the data integrated in the first frame is a three bit word that indicates the length of the variable length command block.

11. The device of claim 7, wherein the peripheral is a memory device.

12. The device of claim 11, wherein the memory device is a redundant array of independent disks.

13. The device of claim 7, wherein the device receives the variable length command block in a dual addressing scheme.

14. A computer program product embodied on a computer readable medium for enabling the receiving of a variable length command block from a PCI bus, the computer program product comprising computer instructions for:

receiving a variable length command block, via the PCI bus, from at least one processor;

locating a first frame within the variable length command block; and

identifying the total number of frames, within the variable length command block, from data integrated within the first frame.

15. The computer program product of claim 14, further comprising computer instructions for:

reading the total number of frames within the variable length command block; and

determining the command within the variable length command block.

16. The computer program product of claim 14, wherein the computer program product runs in firmware associated with a memory device.

17. The computer program product of claim 16, wherein the memory device is a redundant array of independent disks.

18. The computer program product of claim 14, wherein the variable length command block is received in a dual addressing scheme.