Wafer-level package having test terminal
First Claim
1. A wafer-level package comprising:
- a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
an excessive power supply protection element provided in said outer region and between said test chip terminal and said at least one testing member.
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Accused Products
Abstract
A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.
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Citations
8 Claims
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1. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
an excessive power supply protection element provided in said outer region and between said test chip terminal and said at least one testing member.
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2. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
at least one common line provided in said outer region, a plurality of said redistribution traces extending out of a plurality of said semiconductor chip circuit forming regions being connected to said common line, wherein said at least one testing member includes a test pad provided at a part of said common line and exposed from said insulating material.
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3. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
a plurality of units having different functions and provided within said semiconductor chip circuit forming region, a first end of said at least one redistribution trace being connected to one of, or combination of, said units, and a second end of said at least one redistribution trace being connected to said at least one testing member.
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4. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
a test-purpose circuit incorporated in said semiconductor chip circuit forming region, a first end of said at least one redistribution trace being connected to said test-purpose circuit and a second end of said at least one redistribution trace being connected to said at least one testing member.
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5. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
a test-purpose circuit provided in said outer region, wherein said at least one testing member is provided on the test-purpose circuit or on the redistribution trace extending from the test-purpose circuit.
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6. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material;
a test history recording part provided in said outer region and connected to said second end of a plurality of said redistribution traces; and
input/output terminals for writing into/reading out from said test history recording part, said input/output terminals being exposed from said insulating material.
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7. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and
a common line in said outer region, a plurality of said redistribution traces extending out of a plurality of said semiconductor chip circuit forming region being connected to said common line, wherein said at least one testing member includes a test supporting element provided at a part of said common line for testing said semiconductor chip circuit.
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8. A wafer-level package comprising:
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a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to said at least one non-test chip terminal;
at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member; and
an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material, wherein said at least one testing member includes a plurality of test terminals provided with a predetermined rule in such a manner that said semiconductor wafer can be identified from said positions of said test terminals.
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Specification