Semiconductor device and manufacturing method thereof

• US 20060202234A1
• Filed: 02/27/2006
• Published: 09/14/2006
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hara, Akito
• Granted Patent: US 7,847,321 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×10¹⁸ cm⁻³ to 5.0×10¹⁹ cm⁻³, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×10¹⁸ cm⁻³ to 5.0×10¹⁹ cm⁻³. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.

Claims

1. A semiconductor device, comprising:

a field effect transistor; and

a strain generating layer to apply a stress to a channel region of the field effect transistor;

wherein the strain generating layer contains at least one of oxygen and nitrogen of concentration 1.0×

10<sup>18 cm−

3</sup> to 5.0×

10¹⁹ cm<sup>−

3</sup>.

5. The semiconductor device as claimed in claim 1, wherein the concentration peak of the oxygen or the nitrogen resides in the strain generating layer.

2. A semiconductor device, comprising:

a field effect transistor; and

a strain generating layer to apply a stress to a channel region of the field effect transistor;

wherein the strain generating layer contains self-interstitial atoms and/or vacancies of concentration 1.0×

10¹⁸ cm<sup>−

3</sup> to 5.0×

10¹⁹ cm<sup>−

3</sup>, and at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.

3. The semiconductor device as claimed in claim 2, wherein the strain generating layer is a global strain generating layer located under a semiconductor layer in which the channel region exists.

4. The semiconductor device as claimed in claim 2, wherein the strain generating layer is a localized strain generating layer located on both sides of a semiconductor layer in which the channel region exists.

6. The semiconductor device as claimed in claim 2, wherein the concentration peak of the self-interstitial atoms and/or vacancies resides in the strain generating layer.

7. The semiconductor device as claimed in claim 2, wherein the strain generating layer is located in the horizontal direction with respect to the channel region, and applies a uniaxial stress to the channel region.

8. The semiconductor device as claimed in claim 2, wherein the strain generating layer is located in the vertical direction with respect to the channel region, and applies a biaxial stress to the channel region.

9. A semiconductor device manufacturing method comprising the steps of:

forming a strain generating layer in or on a semiconductor substrate so as to apply a stress to a semiconductor layer that is to serve as a channel region of a field effect transistor;

introducing at least one of oxygen and nitrogen to the strain generating layer and/or the semiconductor layer; and

forming the field effect transistor on the semiconductor layer.

10. A semiconductor device manufacturing method comprising the steps of:

forming a strain generating layer in or on a semiconductor substrate so as to apply a stress to a semiconductor layer that is to serve as a channel region of a field effect transistor;

introducing an impurity into the strain generating layer and/or the semiconductor layer to produce self-interstitial atoms, vacancies and clusters thereof; and

forming the field effect transistor on the semiconductor layer.

11. The semiconductor device manufacturing method as claimed in claim 10, wherein the impurity is introduced by ion implantation.

12. The semiconductor device manufacturing method as claimed in claim 10, wherein the impurity includes any one of O, N, C, As, P, Sb, B, Ge, and combinations thereof.

13. The semiconductor device manufacturing method as claimed in claim 10, wherein the impurity is introduced at or below 5.0×

10<sup>14 cm−

2</sup>.

14. The semiconductor device manufacturing method as claimed in claim 10, further comprising the steps of:

forming a groove in a part of a source and drain region of the field effect transistor;

introducing the impurity into the groove so as to cover at least an area in the vicinity of the channel region; and

filling the groove with a material with a lattice constant different from that of the semiconductor substrate to form the strain generating layer.

15. The semiconductor device manufacturing method as claimed in claim 10,

wherein the strain generating layer is formed over the semiconductor substrate;

the impurity is introduced into the strain generating layer; and

the semiconductor layer is formed over the strain layer using a material with a lattice constant different from that of the semiconductor substrate.

16. The semiconductor device manufacturing method as claimed in claim 12, wherein the impurity introducing step includes producing self-interstitial atoms, vacancies, and clusters thereof in the strain generating layer and/or the semiconductor layer.

17. The semiconductor device manufacturing method as claimed in claim 16, wherein the impurity is introduced such that a concentration peak of the self-interstitial atoms, the vacancies , and the clusters thereof exists in the strain generating layer.