Metal gate semiconductor device and manufacturing method

• US 20060202237A1
• Filed: 04/10/2006
• Published: 09/14/2006
• Est. Priority Date: 03/25/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Fu-Liang, Huang, Chien-Chao, Chen, Kuang-Hsin
• Granted Patent: US 7,923,759 B2
• Time in Patent Office: Days
• US Class Current: 257/250
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

Claims

1-7. -7. (canceled)

8. A semiconductor device comprising:

a substrate;

a plurality of first gate electrodes located on the substrate;

a first gate dielectric located between each first gate electrode and the substrate, the first gate dielectrics being substantially the same thickness;

at least one of the first gate electrodes made of a first material;

at least one of the first gate electrodes made of a second material which is different from the first material;

at least one second gate electrode located on the substrate, the at least one second gate electrode being made of either the first material or the second material; and

a second gate dielectric located between each at least one second gate electrode and the substrate, the second gate dielectrics having a thickness different from that of the first gate dielectrics.

9. The semiconductor device of claim 8 wherein the substrate is silicon on insulator.

10. The semiconductor device of claim 8 wherein the first material is polysilicon.

11. The semiconductor device of claim 8 wherein the second material is selected from the group consisting of a metal, a metal alloy, a metal silicide, and a combination thereof.

12. The semiconductor device of claim 8 wherein the second material includes a plurality of materials.

13. The semiconductor device of claim 8 wherein at least one gate dielectric is an oxide.

14. The semiconductor device of claim 8 wherein at least one gate dielectric is a high K material.

15. A semiconductor device comprising:

a substrate;

a plurality of first gate electrodes located on the substrate;

a first gate dielectric located between each first gate electrode and the substrate, the first gate dielectrics being substantially the same thickness;

at least one of the first gate electrodes made of a first material;

at least one of the first gate electrodes made of a second material which is different from the first material;

at least one second gate electrode located on the substrate, the at least one second gate electrode being made of a third material which is different from the first and second material; and

a second gate dielectric located between each at least one second gate electrode and the substrate, the second gate dielectrics having a thickness different from that of the first gate dielectrics.

16. The semiconductor device of claim 15 wherein the substrate is silicon on insulator.

17. The semiconductor device of claim 15 wherein the first material is polysilicon.

18. The semiconductor device of claim 15 wherein the second material is a metal or metal alloy.

19. The semiconductor device of claim 15 wherein the third material is a metal silicide.

20. The semiconductor device of claim 15 further wherein the third material is a plurality of materials.

21. The semiconductor device of claim 15 wherein at least one gate dielectric is an oxide.

22. The semiconductor device of claim 15 wherein at least one gate dielectric is a high K material.

23. A semiconductor device comprising:

a substrate;

a metal gate electrode located on the substrate; and

a plurality of spacers, the plurality of spacers including a first spacer adjacent to the metal gate electrode and a second spacer adjacent to the first spacer.

24. The semiconductor device of claim 23 wherein the metal gate electrode is a metal silicide.

25. The semiconductor device of claim 23 wherein the first spacer or second spacer is selected from the group consisting of SiON, Si₃N₄, SiC, and a combination thereof.

26. A semiconductor device comprising:

a substrate;

a gate electrode located on the substrate;

a first spacer surrounding the gate electrode and spaced apart from the gate electrode to form a first region therebetween; and

a second spacer located both inside and outside of the first region.

27. The semiconductor device of claim 26 wherein the gate electrode is a metal silicide.

28. The semiconductor device of claim 26 wherein the first spacer or second spacer is selected from the group consisting of SiON, Si₃N₄, SiC, and a combination thereof.

29. A semiconductor device comprising:

a substrate;

a gate electrode located on the substrate;

a first spacer located on the substrate and adjacent to the gate electrode;

a second spacer located adjacent the first spacer, which surrounds the gate electrode and is spaced apart from the gate electrode to form a first region therebetween; and

a third spacer located both inside and outside of the first region.

30. The semiconductor device of claim 29 wherein the gate electrode is a metal silicide.

31. The semiconductor device of claim 29 wherein the first spacer is SiO₂.

32. The semiconductor device of claim 29 wherein the second spacer or third spacer is selected from the group consisting of SiON, Si₃N₄, SiC, and a combination thereof.

33-56. -56. (canceled)