Field effect transistor with metal source/drain regions

• US 20060202266A1
• Filed: 03/14/2005
• Published: 09/14/2006
• Est. Priority Date: 03/14/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Radosavljevic, Marko, Majumdar, Amian, Doczy, Mark L., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Datta, Suman
• Application Number:
  US11/080,765
• Publication Number:
  US 20060202266A1
• Time in Patent Office: Days
• US Class Current: 257/344
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Claims

1. A semiconductor device comprising:

a gate electrode formed on a gate dielectric layer formed on a semiconductor channel region of a semiconductor film; and

a pair of source/drain regions formed adjacent to said semiconductor channel region on opposite sides of said gate electrode, said source/drain regions comprising a semiconductor portion adjacent to and in contact with said semiconductor channel and a metal portion adjacent to and in contact with said semiconductor portion.

2. The semiconductor device of claim 1 wherein said semiconductor is silicon and said metal portion is platinum.

3. The semiconductor device of claim 1 wherein said semiconductor is carbon nanotubes and said metal portion is palladium.

4. The semiconductor device of claim 1 wherein said semiconductor channel region is formed on an insulating film of an insulating substrate and wherein said metal portion is formed on said insulating film.

5. The semiconductor device of claim 1 wherein said gate dielectric layer is formed on a first surface of said substrate and wherein said metal portion of said source/drain region is formed beneath said first surface.

6. The semiconductor device of claim 1 further comprising a pair of sidewall spacers formed adjacent to said gate electrode wherein a portion of said metal portion of said source/drain regions is formed beneath said sidewall spacers.

7. The semiconductor device of claim 6 wherein said silicon portion of said source/drain regions is formed beneath said sidewall spacers.

8. A semiconductor device comprising:

a semiconductor body formed on an oxide film formed on a substrate, said semiconductor body having a top surface and a pair of laterally opposite sidewalls;

a gate dielectric layer formed on the top surface and sidewalls of said semiconductor body;

a gate electrode formed on said gate dielectric layer on said top surface of said semiconductor body and on said sidewalls of said semiconductor body, said gate electrode having a pair of laterally opposite sidewalls;

a pair of sidewall spacers formed adjacent to said laterally opposite sidewalls of said gate electrode and on said top surface of said semiconductor body and adjacent to said sidewalls of said semiconductor body;

a pair of source/drain regions each comprising;

a source/drain extension formed in said semiconductor body beneath said sidewalls spacers; and

a metal portion in contact with said source/drain extension.

9. The semiconductor device of claim 8 wherein said metal portion is in contact with said oxide film formed on said substrate.

10. The semiconductor device of claim 8 wherein said metal portion extends beneath said pair of sidewall spacers.

11. The semiconductor device of claim 8 wherein said metal portion is formed from a metal selected from the group consisting of palladium and platinum.

12. The semiconductor device of claim 8 wherein said semiconductor body is silicon and wherein said metal portion is platinum.

13. The semiconductor device of claim 8 wherein said semiconductor body is carbon nanotubes and said metal portion is palladium.

14. A method of forming a semiconductor device comprising:

forming a gate electrode on a gate dielectric layer formed on a channel region of a semiconductor film;

forming a pair of source/drain regions on opposite sides of said gate electrode wherein said source/drain regions comprise a semiconductor portion adjacent to and in contact with said channel region and a metal portion adjacent to and in contact with said semiconductor portion.

15. The method of claim 14 further comprising forming a pair of sidewall spacers adjacent to the sidewalls of said gate electrode;

and

forming said semiconductor portion of said source/drain regions beneath said pair of sidewall spacers.

16. The method of claim 14 wherein said semiconductor film is silicon and said metal portion is platinum.

17. The method of claim 14 wherein said semiconductor film is carbon nanotubes and said metal portion is palladium.

18. A method of forming a transistor comprising:

forming a gate electrode having a pair of laterally opposite sidewalls on a gate dielectric layer formed on a semiconductor layer;

forming a pair of source/drain extensions in said semiconductor layer on opposite sides of said gate electrode;

forming a pair of sidewall spacers adjacent to said sidewalls of said gate electrode and on said source/drain extensions;

forming a pair of source/drain contact regions in said semiconductor layer on opposite sides of said sidewall spacers;

forming an interlayer dielectric adjacent to said sidewall spacers and over said source/drain contact regions;

etching a pair of contact openings through said interlayer dielectric to expose a portion of said source/drain contact regions;

etching away a portion of said source/drain contact regions to form a pair of etched-out source/drain contact regions; and

depositing a metal film into said contact openings and into said etched-out source/drain contact regions.

19. The method of claim 18 wherein said metal film in said etched-out source/drain contact regions directly contact said source/drain extensions.

20. The method of claim 18 wherein said metal film is formed beneath said sidewall spacers.

21. The method of claim 18 wherein said source/drain extensions are formed by ion implanting dopants in alignment with said sidewalls of said gate electrode.

22. The method of claim 18 wherein said source/drain contact regions are formed by ion implanting dopants into said semiconductor film in alignment with the outside edges of said sidewall spacers.

23. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a top surface opposite a bottom surface formed on an insulating layer of an insulating substrate, said semiconductor body having a pair of laterally opposite sidewalls;

forming a gate dielectric layer on the top surface and sidewalls of said semiconductor body;

forming a gate electrode having a pair of laterally opposite sidewalls on said gate dielectric layer and on the top surface of said semiconductor body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body;

forming a pair of source/drain extensions in said semiconductor body on opposite sides of said gate electrode;

forming a pair sidewalls spacers adjacent to said gate electrode and on and adjacent to said source/drain extensions formed in said semiconductor body;

forming a pair of source/drain contact regions in said semiconductor body on opposite sides of said sidewall spacers;

forming an interlayer dielectric layer over and adjacent to said semiconductor body and adjacent to said sidewall spacers;

etching a pair of contact openings through said interlayer dielectric layer to said source/drain contact regions in said semiconductor body;

etching away a portion of said source/drain contact regions in said semiconductor body; and

depositing a metal film in said contact openings and in said etched away portion of said semiconductor body.

24. The method of claim 23 wherein said etching of said portion of said source/drain contact region in said semiconductor body etches until said insulating layer of said insulating substrate is reached.

25. The method of claim 24 wherein said metal film in said etched away portion of said semiconductor body contact said source/drain extension regions.

26. The method of claim 23 wherein said opening in said semiconductor body is larger than the contact opening formed through said interlayer dielectic.