Semiconductor device, semiconductor element and method for producing same

• US 20060202285A1
• Filed: 04/14/2006
• Published: 09/14/2006
• Est. Priority Date: 09/27/1999
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimizu, Kazuhiro, Shirota, Riichiro, Takeuchi, Yuji, Yaegashi, Toshitake, Arai, Norihisa, Kamiya, Eiji
• Application Number:
  US11/403,872
• Publication Number:
  US 20060202285A1
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

Claims

1. A semiconductor device comprising:

a plurality of memory transistors each having a floating gate and a control gate, said memory transistors arranged in column direction being connected to each other in series to form a transistor unit, and one end of the transistor unit being a drain side terminal and the other end of the transistor unit being a source side terminal; and

at least one select gate transistor functioning as a gate for transmitting and receiving data, said select gate transistor connecting said drain side terminal with a bit line or connecting said source side terminal with a source line, a select gate electrode of the select gate transistor being connected to a transistor select line via a gate electrode contact made of polysilicon, a column direction width of the gate electrode contact being wider than a column direction width of the select gate transistor in a plane involving an upper surface of the select gate electrode.

2. The semiconductor device according to claim 1, wherein the select gate transistor is connected with the bit line or the source line via a bit line contact or a source line contact each made of polysilicon.

3. The semiconductor device according to claim 2, wherein the polysilicon of the gate electrode contact and the polysilicon of the bit line contact or the source line contact are the same polysilicon.

4. The semiconductor device according to claim 3, wherein the material of the select gate electrode and the material of the floating gate are the same material.