Semiconductor device with STI and its manufacture

• US 20060202301A1
• Filed: 05/15/2006
• Published: 09/14/2006
• Est. Priority Date: 03/18/2002
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Ohta, Hiroyuki, Iriyama, Yasunori
• Granted Patent: US 7,589,391 B2
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.

Claims

1. A semiconductor device comprising:

a silicon substrate;

an isolation trench formed in said silicon substrate for isolating n-type and p-type active regions in said silicon substrate, said isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate;

a first liner insulating film formed on a surface of said trench surrounding said n-type and p-type active regions and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm;

a second liner insulating film formed on said first liner insulating film surrounding said n-type and p-type active regions and made of a silicon nitride film having a thickness of 2 to 8 nm; and

an isolation region burying said trench defined by said second liner insulating film;

an n-channel MOS transistor formed in said p-type active region;

a p-channel MOS transistor formed in said n-type active region;

wherein an upper end of said second liner insulating film is retracted by less than about 10 nm from the surface of said silicon substrate;

wherein said second liner insulating film has a tensile stress of 1 GPa or larger; and

wherein said first and second liner insulating films extend from side walls of said trench to partially overlay an upper surface of the silicon substrate.

2. A semiconductor device according to claim 1, wherein said isolation region includes a portion extending on said second liner insulating layer above the upper surface of said silicon substrate.

3. A semiconductor device according to claim 2, wherein said second liner insulating film includes a portion extending on side walls of said extending portion of said isolation region.

4. A method of manufacturing a semiconductor device, comprising steps of:

(a) forming a polishing stopper layer on a surface of a silicon substrate, said stopper layer including a lower silicon oxide film and an upper silicon nitride film;

(b) etching said stopper layer and the silicon substrate by using a mask to form a trench;

(c) forming a first liner insulating film on a surface of the silicon substrate exposed in said trench, said first liner insulating film being a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm;

(d) forming a second liner insulating film on said first liner insulating film, said second liner insulating film being made of a silicon nitride film having a thickness of 2 to 8 nm;

(e) depositing an isolation layer on said silicon substrate, said isolation layer burying said trench defined by said second liner insulating film;

(f) polishing and removing an unnecessary portion of said isolation layer by using said stopper layer as a polishing stopper; and

(g) etching said stopper layer.

5. A method according to claim 4, further comprising between said steps (b) and (c) a step of:

(h) side-etching the silicon oxide film of said stopper layer to form retracted portions of the silicon oxide film.

6. A method according to claim 5, wherein thicknesses of the silicon oxide film of said stopper layer and said first and second liner insulating films are set to such values that said retracted portions are not buried by the first and second liner insulating films.

7. A method according to claim 4, further comprising between said steps (b) and (c) a step of:

(i) etching the silicon nitride film of said stopper layer to form retracted portions of the silicon nitride film and partially expose partial upper surfaces of the underlying silicon oxide film.

8. A method according to claim 4, wherein said stopper layer includes, from lower position, a silicon oxide film, an amorphous silicon film and a silicon nitride film and the method further comprises between said steps (b) and (c) a step of:

(j) side-etching the amorphous silicon film to form retracted portions of the amorphous silicon film.

9. A method according to claim 4, wherein said step (d) forms a silicon nitride film having a tensile stress of 1 GPa or larger.

10. A method according to claim 4, wherein said step (g) includes a step of etching the silicon nitride film of said stopper layer by hot phosphoric acid.

11. A method according to claim 4, wherein said step (g) includes a step of etching the silicon oxide film of said stopper layer by dilute hydrofluoric acid or buffered hydrofluoric acid.

12. A method of manufacturing a semiconductor device, comprising steps of:

(a) forming a polishing stopper layer on a surface of a silicon substrate, said stopper layer including a lower silicon oxide film and an upper silicon nitride film;

(b) etching said stopper layer and the silicon substrate by using a mask to form a trench in an isolation region defining active regions;

(c) side-etching the silicon oxide film of said stopper layer to retract side walls of the silicon oxide film;

(d) etching silicon to round a shoulder of the active region exposed by the retracted side wall;

(e) forming a liner insulating film on the surface of the silicon substrate, said liner insulating film being made of a silicon nitride film having a thickness of 2 to 8 nm;

(f) depositing an isolation layer on said silicon substrate, said isolation layer burying said trench defined by said liner insulating film;

(g) polishing and removing an unnecessary portion of said isolation layer by using said stopper layer as a polishing stopper; and

(h) etching said stopper layer.

13. A method according to claim 12, wherein said step (e) forms a silicon nitride film having a tensile stress of 1 GPa or larger.

14. A method according to claim 12, wherein said step (h) includes a step of etching the silicon nitride film by hot phosphoric acid.

15. A semiconductor device comprising:

a silicon substrate with semiconductor elements;

an isolation trench formed in said silicon substrate for isolating active regions in said silicon substrate, said isolation trench having generally a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate and having a gradually broadening upper portion, said isolation trench defining the active regions with rounded shoulders;

a liner insulating film formed in direct contact with a surface of said trench and made of a silicon nitride film having a thickness of 2 to 8 nm; and

an isolation region burying said trench defined by said liner insulating film.

16. A semiconductor device according to claim 15, wherein an upper end of said liner insulating film is retracted by less than about 10 nm from the surface of said silicon substrate.

17. A semiconductor device according to claim 15, wherein said liner insulating film has a tensile stress of 1 GPa or larger.