Method and apparatus for universal program controlled bus architecture

• US 20060202716A1
• Filed: 09/01/2005
• Published: 09/14/2006
• Est. Priority Date: 09/04/1996
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Ting, Benjamin S., Pani, Peter M.
• Granted Patent: US 7,382,156 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

Claims

1. An integrated circuit, comprising:

a programmable logic array comprising;

a plurality of logic cells; and

programmable interconnections to receive digital input signals and to perform logical functions to transmit digital output signals;

a megacell comprising a plurality of functional blocks receiving digital inputs and transmitting digital outputs, wherein the megacell does not exclusively perform a memory function; and

a programmable interconnections subsystem to provide communication between the programmable logic array and the megacell.

2. The integrated circuit as set forth in claim 1, wherein the megacell is implemented using programmed metal masks.

3. The integrated circuit as set forth in claim 1, wherein the megacell is implemented using customized masks.

16. The integrated circuit as set forth in claim 11, wherein each of the plurality of megacells is a dual port SRAM block.

17. The integrated circuit as set forth in claim 16, wherein two or more of the plurality of megacells are cascaded to form a single dual port SRAM block being deeper than one of the plurality of megacells.

18. The integrated circuit as set forth in claim 16, wherein two or more of the plurality of megacells are cascaded to form a single dual port SRAM block being wider than one of the plurality of megacells.

19. The integrated circuit as set forth in claim 16, wherein four or more of the plurality of megacells are cascaded to form a single dual port SRAM block being deeper and wider than one of the plurality of megacells.

20. The integrated circuit as set forth in claim 19, wherein the routing resources comprise interconnection lines.

21. The integrated circuit as set forth in claim 19, wherein each of the first and second groups of routing resources are programmable through switches.

4. A method, comprising:

performing a processing function by a megacell; and

communicating digital signals between the megacell and a programmable logic array using a programmable interconnection subsystem.

5. The method of claim 4, further comprising selecting, within the programmable interconnection subsystem, one of the digital signals using tri-statable logic control for at least one of input to or output from the megacell.

6. The method of claim 4, further comprising selecting, within the programmable interconnection subsystem, one of the digital signals using tri-statable logic control for at least one of input to or output from the programmable logic array.

7. The method of claim 4, further comprising programming the programmable interconnection subsystem to enable the communicating of the digital signals.

8. The method of claim 6, further comprising providing a tri-state to the logic control in the programmable interconnection subsystem to enable the communicating.

9. An integrated circuit, comprising:

a programmable logic array comprising;

a plurality of logic cells, wherein the logic cells are organized in two dimensions; and

a first one or more routing resources selectively coupled to the plurality of logic cells;

a second one or more routing resources located adjacent to the programmable logic array the second one or more routing resources being different than the first one or more routing resources;

a plurality of megacells configured to receive inputs and transmit outputs;

wherein each of the plurality of megacells is selectively coupled to the second one or more routing resources; and

wherein the second one or more routing resources are selectively coupled to the programmable logic array.

10. The integrated circuit as set forth in claim 9, wherein each of the plurality of megacells is selectively coupled to the programmable logic array.

11. The integrated circuit as set forth in claim 10, wherein the second one or more routing resources are selectively coupled to at least one of the programmable logic array and each of the plurality of megacells through logic controlled three-stable outputs.

12. The integrated circuit as set forth in claim 11, wherein each of the plurality of megacells comprises a memory block.

13. The integrated circuit as set forth in claim 12, wherein two or more of the plurality of megacells are cascaded to form a single memory block being deeper than one of the plurality of megacells.

14. The integrated circuit as set forth in claim 12, wherein two or more of the plurality of megacells are cascaded to form a single memory block being wider than one of the plurality of megacells.

15. The integrated circuit as set forth in claim 12, wherein four or more of the plurality of megacells are cascaded to form a single memory block being deeper and wider than one of the plurality of megacells.

22. A method of operating an integrated circuit having a programmable logic array, comprising:

selectively coupling a first one or more routing resources to a plurality of logic cells of the programmable logic array, wherein the logic cells are organized in two dimensions, wherein a second one or more routing resources is located adjacent to the programmable logic array, the second one or more routing resources being different than the first one or more routing resources;

receiving inputs to and transmitting outputs from a plurality of megacells;

selectively coupling each of the plurality of megacells to the second one or more routing resources; and

selectively coupling the second one or more routing resources to the programmable logic array.

23. The method of claim 22, further comprising selectively coupling the plurality of megacells to the programmable logic array.

24. The method of claim 23, further comprising selectively coupling the second one or more routing resources to at least one of the programmable logic array and the megacells through logic controlled three-stable outputs.

25. The method of claim 24, wherein each of the plurality of megacells comprises a memory block.

26. The method of claim 25, further comprising cascading two or more of the plurality of megacells to form a single memory block being deeper than one of the plurality of megacells.

27. The method of claim 26, wherein cascading comprises selectively coupling data buses of the second one or more routing resources.

28. The method of claim 25, further comprising cascading two or more of the plurality of megacells to form a single memory block being wider than one of the plurality of megacells.

29. The method of claim 28, wherein cascading comprises selectively coupling address buses of the second one or more routing resources.

30. The method of claim 25, further comprising cascading four or more of the plurality of megacells to form a single memory block being deeper and wider than one of the plurality of megacells.

31. The method of claim 30, wherein cascading comprises selectively coupling data buses and address buses of the second one or more routing resources.

32. The method of claim 25, further comprising cascading two or more of the plurality of megacells to form a single dual port SRAM block being deeper than one of the plurality of megacells.

33. The method of claim 32, wherein cascading comprises selectively coupling data buses of the second one or more routing resources.

34. The method of claim 25, further comprising cascading two or more of the plurality of megacells to form a single dual port SRAM block being wider than one of the plurality of megacells.

35. The method of claim 34, wherein cascading comprises selectively coupling address buses of the second one or more routing resources.

36. The method of claim 25, further comprising cascading four or more of the plurality of megacells to form a single dual port SRAM block being deeper and wider than one of the plurality of megacells.

37. The method of claim 36, wherein cascading comprises selectively coupling data buses and address buses of the second one or more routing resources.