SYSTEMS AND METHODS THAT EMPLOY INDUCTIVE CURRENT STEERING FOR DIGITAL LOGIC CIRCUITS

• US 20060202723A1
• Filed: 05/18/2006
• Published: 09/14/2006
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Notthoff, Johannes K.
• Granted Patent: US 7,272,071 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03K 17/04113 in bipolar transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration

Abstract

The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is “on” while the other is “off,” which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters. Further, the systems and methods can be utilized to construct flip-flops and shift registers by coupling differential transistor pairs and driving these pairs with the transformer-based single-ended or differential clock.

Claims

1. A shift register that employs inductive current switching, comprising:

a plurality of flip-flops; and

a clock bus that induces current, which defines state of respective flip-flops.

2. The shift register of claim 1, the plurality of flip-flops are serially coupled via routing at least one output of one flip-flop to at least one input of a succeeding flip-flop.

3. The shift register of claim 1, at least one flip-flop is configured with a fanout of one.

4. The shift register of claim 1, the clock bus comprises at least one transformer that generates the induced current.

5. The shift register of claim 1, each of the flip-flops is an inductive current steering-based flip-flop.

6. The shift register of claim 1, the inductive currents comprise at least two currents that are 180 degrees out of phase with respect to one another.

7. The shift register of claim 1, each of the flip-flops comprising a plurality of data latches connected in series and driven by the clock bus.

8. The shift register of claim 7, the clock bus is a transformer based clock bus comprising at least one transformer for each respective transistor of the plurality of data latches, respective transformers provide inductive current to respective transistors and the inductive current defines the state of the respective flip-flops.

9. The shift register of claim 7, each of the data latches comprise a track differential transistor pair and a hold differential transistor pair.

10. A inductive current-based data latching method, comprising:

coupling at least two data latches in series;

employing a transformer based clock bus that induces current; and

routing the induced current to the at least two data latches to track and hold data within the data latches.

11. The method of claim 10 is employed in connection with one or more of a register, a flip-flop, a frequency divider, a memory module, a latch, a multiplexer, an oscillator, a power amplifier, an RF integrated circuit, and an ASIC.

12. The method of claim 10, differential clock signals are utilized to provide differential signals to at least two inputs of the transformer based clock bus.

13. The method of claim 12, the current induced in respective secondary windings of the transformer is 180 degrees out-of-phase.

14. The method of claim 13, the inputs are utilized to reverse the induced current phase which provides a differential output signal.

15. The method of claim 10, a signal from the clock bus is toggled to provide for tracking and holding data via the latches.

16. The method of claim 10, employed in a X-bit shift register, where X is an integer.

17. The method of claim 16, further comprising:

forming a plurality of flip-flops from the serially coupled data latches;

coupling the X flip-flops via routing the outputs associated with one flip-flop to the inputs of the following flip-flop;

employing a transformer based clock bus to drive the X-bit Register;

loading the last flip-flop with a fanout of one.

18. A shift register, comprising:

means for receiving a clock signal;

means for generating an inductive current based on the clock signal; and

means for steering the inductive current through the differential transistor pair in order to effectuate the output state of the differential transistor pair;

means for employing the output of the differential transistor pair to track and hold data.

19. The shift register of claim 18, the clock signal is employed to toggle the output of the differential transistor pair.

20. The shit register of claim 18, the differential transistor pair comprises at least one of an Indium Phosphide (InP), a carbon-doped InP, an Indium Gallium Arsenide (InGaAs), a GaAs, and an Aluminum Gallium Arsenide (AlGaAs) transistor.