DEVICE AND METHOD FOR COMPENSATING DEFECT IN SEMICONDUCTOR MEMORY

• US 20060203579A1
• Filed: 12/27/2005
• Published: 09/14/2006
• Est. Priority Date: 02/11/2004
• Status: Active Grant

• Current Assignee: Jun-Lin Yeh
• Original Assignee: Jun-Lin Yeh
• Inventors: Yeh, Jun-Lin
• Granted Patent: US 7,203,107 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity

Abstract

A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.

Claims

1. A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, said device comprising:

a memory array, comprising at least a defectless sub-memory region, said memory array being coupled to an address decoder circuit and a sensing circuit for storing data;

a selection circuit, coupled to a control unit, outputting a selection signal to said control unit; and

a first input address buffer, coupled to said control unit and the address decoder circuit, outputting an address signal to said address decoder circuit in response to said selection signal for selecting said defectless sub-memory region to store data.

2. The device of claim 1, further comprising a chip identification circuit coupled to said control unit, said chip identification circuit including an output terminal, a whole signal terminal, and a partial signal terminal, said chip identification circuit enabling one of said whole signal terminal and said partial signal terminal to output an identification signal at said output terminal to represent a memory size of said semiconductor memory.

3. The device of claim 1, further comprising a second input address buffer coupled to said address decoder circuit and said control unit, said second input address buffer including a plurality of address input ports and a plurality of address output ports, said plurality of address input ports receiving a plurality of address signals except a most significant bit address signal from said first input address buffer and sending said plurality of address signals to said address decoder circuit.

4. The device of claim 3, wherein said selection circuit includes:

an enable circuit, having an enable signal output terminal, wherein said enable circuit sends an enable signal via said control unit to said first input address buffer to determine said first input address buffer and outputs one of said most significant bit address signal and said selection signal;

a region selection circuit, coupled to said control unit, wherein when said memory region has said defect, said region selection circuit sending said selection signal via said control unit to said first input address buffer to select said defectless sub-memory region to store data; and

a NAND gate, having two input terminals and an output terminal, wherein one of said two input terminals of said NAND gate is coupled to said enable circuit to receive said enable signal, the other of said two input terminals of said NAND gate receives said control signal, and said output terminal of said NAND gate outputs a first buffer control signal to said first input address buffer via said control unit.

5. The device of claim 4, wherein said first input address buffer includes:

a NOR gate, having two input terminals and an output terminal, wherein one of said two input terminals of said NOR gate receives said first buffer control signal, the other of said two input terminals of said NOR gate receives said most significant bit address signal;

a first transmission gate module, having an input terminal and an output terminal, wherein said input terminal of said first transmission gate is coupled to said output terminal of said NOR gate, and said output terminal of said first transmission gate is coupled to said address decoder circuit;

a second transmission gate module, having an input terminal and an output terminal, wherein said input terminal of said second transmission gate receives said selection signal, said output terminal of said second transmission gate is connected to said output terminal of said first transmission gate module and coupled to said address decoder circuit; and

a first inverter, having an input terminal and an output terminal, wherein said input terminal of said first inverter receives said enable signal, said output terminal of said first inverter is coupled to said first transmission gate module and said second transmission gate module.

6. The device of claim 5, wherein said first transmission gate module includes:

a second inverter, having an input terminal and an output terminal, wherein said input terminal of said second inverter is coupled to said output terminal of said NOR gate; and

a first transmission gate, having an input terminal, an output terminal, an N-type MOS terminal and a P-type MOS terminal, wherein said input terminal of said first transmission gate is coupled to said output terminal of said second inverter, said N-type MOS terminal of said first transmission gate receives said enable signal, said P-type MOS terminal of said first transmission gate is coupled to said output terminal of said first inverter, said output of said first transmission gate is coupled to said address decoder circuit.

7. The device of claim 6, wherein said second transmission gate module includes:

a second transmission gate, having an input terminal, an output terminal, an N-type MOS terminal and a P-type MOS terminal, wherein said input terminal of said second transmission gate receives said selection signal, said P-type MOS terminal of said second transmission gate receives said enable signal, said N-type MOS terminal of said second transmission gate is coupled to said output terminal of said first inverter, said output terminal of said second transmission gate is connected to said output terminal of said first transmission gate and coupled to said address decoder circuit.

8. The device of claim 4, wherein said selection signal is an address-fixed address signal.

9. The device of claim 1, wherein the number of said sub-memory regions is a base 2 multiple exponential, said multiple is a positive integral.

10. A method for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, said semiconductor memory including a memory region to store data and an address input port for inputting an address signal, said memory region further including at least a defectless sub-memory region, said address signal determining a location of said data in said memory region, said method comprising:

determining whether or not said memory region of said semiconductor memory has a defect; and

replacing said memory region with said defectless sub-memory region to store said data when said semiconductor memory is defective.

11. The method of claim 10, wherein said step of replacing said memory region with said defectless sub-memory region to store said data includes:

disabling a most significant bit address of said address input port; and

replacing said most significant bit address with a selection signal to select said defectless sub-memory region.

12. The method of claim 11, wherein said step of replacing said memory region with said defectless sub-memory region to store said data further includes:

modifying an identification code of said semiconductor memory to represent a modified size of said semiconductor memory.