Method for fabricating metal oxide semiconductor with lightly doped drain

• US 20060205126A1
• Filed: 10/24/2005
• Published: 09/14/2006
• Est. Priority Date: 03/09/2005
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Yen, Shih-Yi
• Granted Patent: US 7,309,625 B2
• Time in Patent Office: Days
• US Class Current: 438/163
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method for fabricating metal oxide semiconductor with lightly doped drain. In the method, the gate electrode, the LDD of the n-type MOS TFT, and the source/drain electrode of the p-type MOS TFT are defined simultaneously in one photolithography step. The contact holes and the source/drain electrode of the n-type MOS TFT are also defined simultaneously in one photolithography step. The invention employs only six photolithography steps to manufacture the metal oxide semiconductor, such as TFT, with lightly doped drain, thereby avoiding alignment errors, further improving yield and increasing throughput.

Claims

1. A method for fabricating metal oxide semiconductor (MOS) with lightly doped drain (LDD), comprising:

providing a substrate with a p-type MOS TFT region and an LDD region defined thereon;

forming a first semiconductor island in the LDD region and a second semiconductor island in the p-type MOS TFT region, wherein the first semiconductor island comprises a channel region, a predetermined lightly doped regions and a predetermined source/drain region, and the second semiconductor island comprises a channel region and a predetermined source/drain region;

forming a gate insulating layer and a conductive layer on the substrate sequentially;

forming a first patterned mask layer directly on the conductive layer over the first semiconductor island and the channel region of the second semiconductor island, wherein the first patterned mask layer over the channel regions of the first and second semiconductor island is thicker than the first patterned mask layer over the predetermined lightly doped regions and predetermined source/drain region of the first semiconductor island;

etching the conductive layer to form a patterned conductive layer, with the first patterned mask layer acting as mask;

performing a heavily doped p-type ion implantation on the predetermined source/drain region of the second semiconductor islands to form a source/drain electrode in the p-type MOS TFT region;

removing the patterned conductive layer over the predetermined lightly doped regions and predetermined source/drain region of the first semiconductor island;

performing a lightly doped n-type ion implantation on the predetermined lightly doped regions of the first semiconductor island, forming lightly doped regions;

removing the remaining first patterned mask layer;

forming a dielectric layer on the substrate;

etching the dielectric layer to form a via hole and a blind hole, wherein the via hole exposes the predetermined source/drain region of the first semiconductor islands, and the blind hole is formed above the source/drain electrode in the p-type MOS TFT region; and

performing a heavily doped n-type ion implantation on the predetermined source/drain region of the first semiconductor islands, forming a source/drain electrode in the LDD region through the via hole.

2. The method as claimed in claim 1, further comprising, before forming a first semiconductor island and a second semiconductor island on the substrate, forming a buffer layer on the substrate.

3. The method as claimed in claim 1, wherein the ion dosage of the heavily doped p-type ion implantation is a hundred times more than that of the lightly doped n-type ion implantation.

4. The method as claimed in claim 1, wherein the first patterned mask layer is formed by using a halftone mask.

5. The method as claimed in claim 1, further comprising:

etching the dielectric layer and the gate insulating layer through the via hole and the blind hole to form a plurality of first contact holes, exposing at least part of the source/drain electrodes;

forming source and drain contacts in the first contact holes;

forming a protection layer on the substrate with second contact holes passing through the protection layer, exposing the source and drain contacts; and

forming a pixel electrode electrically connecting to the source/drain electrode through the source and drain contacts.

6. The method as claimed in claim 1, further comprising, after forming the first contact hole:

forming a silicon nitride layer on the substrate;

performing a thermal process on the substrate; and

removing the silicon nitride layer.

7. The method as claimed in claim 6, wherein the thickness of the silicon nitride layer is in the range between 500 Å

and 2000 Å

.

8. The method as claimed in claim 1, further comprising applying a second patterned mask layer with a step profile before etching the dielectric layer to form a via hole and a blind hole.

9. The method as claimed in claim 8, wherein the second patterned mask layer of variable thickness is formed by using halftone mask.

10. A liquid crystal display, comprising a metal oxide semiconductor fabricated by the method as claimed in claim 1.