Method for producing a semiconductor device and resulting device

• US 20060205161A1
• Filed: 01/30/2006
• Published: 09/14/2006
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Ruythooren, Wouter, Das, Johan
• Granted Patent: US 7,442,635 B2
• Time in Patent Office: Days
• US Class Current: 438/284
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0104 Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According to the method, the interconnect between the source contacts is not produced by air bridge structures, but by etching vias through the semiconductor layer directly to the ohmic contacts and applying a contact layer on the backside of the device.

Claims

1. A method for producing a semiconductor device comprising a plurality of groups consisting of a source, drain and gate contact, or a plurality of groups of an emitter, base and collector contact, wherein the respective types of contact of said groups are interconnected to a common gate, drain and source (or base, collector, emitter) contact, said method comprising the steps of:

providing a first substrate, comprising on its front side a semiconductor layer, and on top of that layer, i.e. on the front side of said layer, a plurality of gate or base contacts, each gate contact lying in between source and drain ohmic contacts, or each base contact lying in between emitter and collector ohmic contacts,

etching vias through the backside of said semiconductor layer, wherein vias are produced directly on top of each contact of at least one type, e.g. on top of all the source ohmic contacts, to thereby expose said ohmic contacts,

producing on the backside of said semiconductor layer an interconnecting contact layer to provide an interconnect between said source-gate-drain groups or emitter-base-collector groups, this resulting in a semiconductor device on the second substrate.

2. The method according to claim 1, wherein vias are produced on top of all the contacts of one type, and the other contacts are connected to lateral areas.

3. The method according to claim 2, wherein vias are produced through the backside of the semiconductor layer, on top of said lateral areas.

4. The method according to claim 1, wherein vias are produced directly on top of all the source contacts, and wherein vias are also produced directly on top of all the drain contacts.

5. The method according to any claim 1, said method comprising the steps of:

providing a first substrate, comprising on its front side a semiconductor layer, and on top of that layer a plurality of gate or base contacts, each gate contact lying in between source and drain contacts, or each base contact lying in between emitter and collector contacts,

providing a second substrate provided with an adhesive layer,

attaching the first substrate to the second, by attaching the front side of said first substrate, including said gate/source/drain or base/emitter/collector contacts, to said adhesive layer of the second substrate,

after the step of attaching the first substrate, and before the step of producing said vias, removing the first substrate from the semiconductor layer, to expose the backside of the semiconductor layer.

after the step of producing vias, producing on the backside of said semiconductor layer an interconnecting contact layer to provide an interconnect between said source-gate-drain groups or emitter-base-collector groups, this resulting in a semiconductor device on the second substrate.

6. The method according to claim 5, wherein said adhesive layer consists of a thermally conductive adhesive layer material selected from the group consisting of organic polymers, thermally conductive epoxy (e.g. epoxies with fillers), SU-8, poly-imide, BCB, silicones, flowable oxides.

7. The method according to claim 5, further comprising the step of applying a contact metal layer onto said contacts, prior to attaching the first substrate to the second.

8. The method according to any one of claims 5, further comprising applying a passivation and heat spreading layer onto said contacts or onto said contact metal layer, prior to attaching the first substrate to the second.

9. The method according to claim 8, wherein said passivation and heat spreading layer consists of AlN, AlSiC, highly resistive Si, SiC or Si-nitride.

10. The method according to claim 5, wherein a passivation layer is applied onto said contacts, and a heat spreading layer is applied onto said passivation layer.

11. The method according to claim 5, further comprising the step of applying a passivation layer on the backside of the semiconductor layer, after the step of producing vias in the semiconductor layer, and before the step of producing the interconnecting contact layer.

12. The method according to claim 5, wherein said semiconductor device is a multiple gate-finger HEMT.

13. The method according to claim 5, wherein said semiconductor device is a multiple base bipolar transistor.

14. The method according to 5, further comprising:

providing a third substrate provided with a bonding layer,

attaching the second substrate to the third substrate, by attaching the side of the second substrate, including said semiconductor device, to said bonding layer on the third substrate,

removing the second substrate and the adhesive layer, this resulting in a semiconductor device on the third substrate.

15. The method according to claim 14, wherein a passivation layer and an etch stop layer are produced on said gate/source/drain (or base/emitter/collector) contacts, prior to attaching the first substrate to the second, and wherein the second substrate and the adhesive layer are removed by an etching process, stopped by the etch layer.

16. The method according to claim 14, further comprising the step of producing heat sinks, on top of said source, gate and drain (or emitter, base, collector) contacts, after removing the second substrate.

17. The method according to claim 14, wherein said vias are produced for contacting only one type of contact (e.g. source, drain, or gate).

18. The method according to claim 5, wherein said first substrate is diced to form individual devices, before the first substrate, in the form of these individual devices, is attached to the second.

19. The method according to claim 14, wherein said second substrate is diced to form individual devices, before the second substrate, in the form of these individual devices, is attached to the third.

20. The method according to claim 1, wherein said semiconductor layer consists of a stack of a GaN layer and an AlGaN layer.

21. The method according to claim 1, wherein said vias are produced through said first substrate, and wherein after producing said vias, said interconnecting layer is produced on the backside of said first substrate.

22. The method according to claim 21, wherein said first substrate is subjected to a thinning operation, before producing said vias.

23. The method according to claim 21, wherein said device is attached to a second substrate, by attaching the backside of said first substrate, including the interconnecting layer, to another substrate.

24. A semiconductor device produced according to the method of claim 1.