DMA engine for protocol processing

• US 20060206635A1
• Filed: 03/10/2006
• Published: 09/14/2006
• Est. Priority Date: 03/11/2005
• Status: Abandoned Application

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Quattromani, Marc Alan, Rekow, Alexander, Alexander, Thomas
• Application Number:
  US11/373,858
• Publication Number:
  US 20060206635A1
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A DMA engine, includes, in part, a DMA controller, an associative memory buffer, a request FIFO accepting data transfer requests from a programmable engine, such as a CPU, and a response FIFO that returns the completion status of the transfer requests to the CPU. Each request includes, in part, a target external memory address from which data is to be loaded or to which data is to be stored; a block size, specifying the amount of data to be transferred; and context information. The associative buffer holds data fetched from the external memory; and provides the data to the CPUs for processing. Loading into and storing from the associative buffer is done under the control of the DMA controller. When a request to fetch data from the external memory is processed, the DMA controller allocates a block within the associative buffer and loads the data into the allocated block.

Claims

1. An apparatus comprising:

a direct memory access controller configured to write data to or retrieve data from a random access memory (RAM) unit; and

an associative memory buffer coupled to direct memory access controller and configured to store the data retrieved from the RAM unit or data to be stored in the RAM unit.

2. The apparatus of claim 1 further comprising:

a first request first-in-first-out (FIFO) configured to store a plurality of data transfer requests from a processor unit; and

a first response FIFO configured to store completion status of a second plurality of data transfer requests.

3. The apparatus of claim 2 wherein each data transfer request comprises an address in the RAM unit, a block size specifying amount of data to be transferred, and context information.

4. The apparatus of claim 1 wherein said associative memory buffer comprises N ports, the apparatus further comprising:

N request first-in-first-out (FIFO) buffers configured to store a plurality of data transfer requests from one or more processor units; and

M response FIFO buffers configured to store completion status of a second plurality of data transfer requests from the one or more processor units.

5. The apparatus of claim 4 wherein M is one.

6. The apparatus of claim 3 wherein said direct memory access controller is configured to inspect contents of the associative memory buffer prior to loading data from the RAM unit or storing data in the RAM unit.

7. The apparatus of claim 6 wherein in response to a load request from the processor unit, the direct memory access controller is caused to return an immediate response if the requested data is present in the associative buffer.

8. The apparatus of claim 7 wherein in response to a store request from the processor unit, the direct memory access controller is caused to take no action if the associative buffer indicates that the requested data has not been modified since it was fetched from external memory.

9. The apparatus of claim 8 wherein said context information is configured to enable the requests to be uniquely identified and further to be correlated to returned responses.

10. The apparatus of claim 9 wherein said context information is further configured to enable the requests to be uniquely identified and further to be correlated to returned responses.

11. The apparatus of claim 1 wherein said associative memory buffer comprises N ports, the apparatus further comprising:

a plurality of request first-in-first-out (FIFO) buffers configured to store a plurality of data transfer requests from a plurality of processor units; and

a plurality of response FIFO buffers configured to store completion status of a second plurality of data transfer requests from the plurality of processor units, wherein each data transfer request comprises an address in the RAM unit, a block size specifying amount of data to be transferred, and context information.

12. The apparatus of claim 11 wherein said context information is further configured to enable context switching between a plurality of concurrent threads operating in parallel on the plurality of processors.

13. The apparatus of claim 12 wherein said RAM unit is external to the DMA engine.

14. The apparatus of claim 13 wherein said associative memory buffer comprises a tag compare logic configured to perform a reduced number of compare operation on its associated tags and in accordance with a working set defined by the context information.

15. A method of processing data, the method comprising:

receiving a request to fetch data from an address in a first memory;

allocating a block of an associative memory to hold the fetched data;

loading the fetched data in the allocated block.

16. The method of claim 15 wherein said request comprises an address in the first memory, a block size specifying the size of the allocated block, and context information.

17. The method of claim 16 further comprising:

storing the context information associated with the request in a second memory.

18. The method of claim 17 further comprising:

reading the stored context information from the second memory;

accessing the requested data from the first memory address;

trapping the requested access; and

directing the read request to allocated block of the associative memory buffer.

19. The method of claim 18 further comprising:

retiring the read request; and

freeing the allocated space in the associative memory buffer.

20. The method of claim 19 wherein said second memory is a first-in-first-out (FIFO) buffer, the method further comprising:

storing the request in a first one of a first one of a plurality of FIFO buffers; and

storing a completion status associated with the request in a second one of a plurality of FIFO buffers.

21. The method of claim 20 wherein said associative memory buffer comprises N ports, the method further comprising:

storing a first plurality of requests in said first plurality of FIFOs; and

storing a first plurality of completion status in said second plurality of FIFO.

22. The method of claim 21 further comprising:

inspecting contents of the associative memory buffer prior to loading data from the first memory or storing data to the first memory.

23. The method of claim 22 further comprising:

returning an immediate response if the requested data is detected as being present in the associative buffer upon the inspection.

24. The method of claim 23 further comprising:

causing no further action if the associative buffer indicates that the requested data has not been modified since it was fetched from first memory.

25. The method of claim 24 said context information is configured to enable the requests to be uniquely identified and further to be correlated to returned responses.

26. The method of claim 25 further comprising:

enabling context switching between a plurality of concurrent threads operating in parallel.

27. The method of claim 26 further comprising:

performing a reduced number of tag compare operation in accordance with a working set defined by the context information.