Packet processing in switched fabric networks

• US 20060206655A1
• Filed: 12/10/2004
• Published: 09/14/2006
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Mitchell, James, Chappell, Christopher L.
• Granted Patent: US 8,285,907 B2
• Time in Patent Office: Days
• US Class Current: 710/315
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

Methods and apparatus, including computer program products, implementing techniques for forming an Advanced Switching (AS) packet by applying AS path binding information to a packet received over a Peripheral Component Interconnect-Express (PCIe) fabric according to a downstream port identifier associated with the packet, and sending the AS packet to an AS fabric. Methods and apparatus, including computer program products, implementing techniques for processing an AS packet received over an AS fabric by comparing an AS payload of the AS packet with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing an AS header from the AS packet to reveal the base packet.

Claims

1. A communication device operable as a virtual Peripheral Component Interconnect-Express (PCIe) switch having an upstream port and N downstream ports, the device comprising:

a first interface to a PCIe fabric to pass communication between the PCIe fabric and the device;

a second interface to an Advanced Switching (AS) fabric to pass communication between the device and the AS fabric; and

a downstream tunneling processor to process packets received through the first interface, the processing of each received packet comprising applying AS path binding information to the received packet according to a downstream port identifier associated with the received packet.

2. The device of claim 1, further comprising:

one or more configuration registers, each configuration register defining a memory space associated with a port identifier.

3. The device of claim 2, wherein:

the memory space associated with a port identifier comprises at least one of a memory window, an I/O window, and a configuration space.

4. The device of claim 1, further comprising:

one or more binding registers, each binding register to include path information binding a downstream port identifier to another device on the AS fabric.

5. The device of claim 1, further comprising:

a PCIe downstream queue disposed between the first interface and the downstream tunneling processor, the PCIe downstream queue to provide buffer space for packets received over the PCIe fabric.

6. The device of claim 5, wherein:

the PCIe downstream queue comprises a first-in-first-out (FIFO) data structure.

7. The device of claim 1, further comprising:

an upstream tunneling processor to process an AS packet received through the second interface.

8. The device of claim 7, further comprising:

an upstream queue in communication with the downstream tunneling processor and the upstream tunneling processor, the upstream queue to provide buffer space for base packets to be transmitted over the PCIe fabric.

9. The device of claim 7, further comprising:

an upstream queue arbiter in communication with the downstream tunneling processor and the upstream tunneling processor, the upstream queue arbiter to arbitrate access to the upstream queue between the downstream tunneling processor and the upstream tunneling processor.

10. The device of claim 7, further comprising:

a downstream queue arbiter in communication with the downstream tunneling processor and the upstream tunneling processor, the downstream queue arbiter to arbitrate access to the AS tunneling interface between the downstream tunneling processor and the upstream tunneling processor.

15. The method of claim 11, further comprising:

processing AS packets received over an AS fabric, each AS packet comprising an AS header and an AS payload, the processing of each AS packet comprising comparing the AS payload with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing the AS header from the AS packet to reveal the base packet.

11. A method comprising:

processing packets received over a first fabric for transmission over a second fabric, the processing of each received packet comprising applying Advanced Switching (AS) path binding information to the received packet according to a downstream port identifier associated with the received packet.

12. The method of claim 11, wherein the first fabric is a Peripheral Component Interconnect-Express (PCIe) fabric and the second fabric is an AS fabric.

13. The method of claim 11, wherein the processing further comprises:

forming an AS packet from the applied AS path binding information and the received packet; and

sending the AS packet to an AS fabric.

14. The method of claim 11, wherein the processing further comprises:

comparing an address identifier of the received packet with one or more memory spaces associated with port identifiers to determine whether the received packet is to be forwarded downstream, and if so, selecting a downstream port identifier based on the comparison.

16. An article comprising a machine-readable medium for use in communicating with an Advanced Switching (AS) fabric, the instructions causing a machine to:

process packets received over a Peripheral Component Interconnect-Express (PCIe) fabric, the instructions to process each received packet comprising instructions to apply AS path binding information to the received packet according to a downstream port identifier associated with the received packet.

17. The article of claim 16, further comprising instructions to:

compare an address identifier of the received packet with one or more memory spaces associated with port identifiers to determine whether the received packet is to be forwarded downstream, and if so, select a downstream port identifier based on the comparison.

18. The article of claim 16, wherein the instructions to apply AS path binding information to the received packet comprise instructions to:

form an AS packet from the applied AS path binding information and the received packet; and

send the AS packet to the AS fabric.

19. The article of claim 16, further comprising instructions to:

process AS packets received over the AS fabric, each AS packet comprising an AS header and an AS payload, the instructions to process each AS packet comprising instructions to compare the AS payload with one or more memory spaces associated with port identifiers, determine whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, remove the AS header from the AS packet to reveal the base packet.

20. A system operative as a virtual Peripheral Component Interconnect-Express (PCIe) switch having an upstream port and N downstream ports, the system comprising:

a PCIe fabric;

a first interface to the PCIe fabric to pass communication between the PCIe fabric and the device;

a second interface to an Advanced Switching (AS) fabric to pass communication between the device and the AS fabric; and

a volatile memory operative to store instructions to process packets received through the first interface, wherein the instructions to process each received packet comprise instructions to apply AS path binding information to the received packet according to a downstream port identifier associated with the received packet.

21. The system of claim 20, wherein the instructions to process each received packet further comprise instructions to:

compare an address identifier of the received packet with one or more memory spaces associated with port identifiers to determine whether the received packet is to be forwarded downstream, and if so, select downstream port identifier based on the comparison.