System and method for optimizing interconnections of memory devices in a multichip module

• US 20060206667A1
• Filed: 05/10/2006
• Published: 09/14/2006
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Kevin J. Ryan
• Original Assignee: Kevin J. Ryan
• Inventors: Ryan, Kevin J.
• Granted Patent: US 7,805,586 B2
• Time in Patent Office: Days
• US Class Current: 711/115
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Claims

1-69. -69. (canceled)

70. A memory module comprising;

a substrate;

a memory hub on the substrate operable to receive memory signals from a memory link port and apply memory signals to the memory link port, the memory signals comprising at least one of command, address or data signals, the memory hub being further operable to translate between memory signals and at least one of electrical command, address or data signals;

a plurality of memory devices on the substrate, the memory devices electrically coupled to the memory hub to receive at least one of command, address, or data signals from the memory hub and to provide data signals to the memory hub;

a first bus coupling a first one of the memory devices to the memory hub;

a second bus coupling a second one of the memory devices to the memory hub;

the first and second buses having substantially a same length, the length being substantially equal to a shortest distance between the memory hub and the first one of the memory devices.

71. The module of claim 70 wherein each of the plurality of memory devices are located substantially equidistant from the memory hub.

72. The module of claim 70 wherein the memory hub is located at an interior of the circuit board.

73. The module of claim 72 wherein the plurality of memory devices are located at a periphery of the circuit board.

74. The module of claim 70 wherein the plurality of memory devices comprise more than two memory devices.

75. The module of claim 70 wherein the plurality of memory devices comprise more than four memory devices.

76. The module of claim 70 wherein the memory link port comprises at least one unidirectional high speed port operable to receive at least one of command, address and write data signals.

77. The module of claim 70 wherein the memory link port comprises at least one unidirectional high speed port operable to transmit at least one of command and read data signals.

78. The module of claim 70, wherein the substrate comprises a circuit board.

79. The module of claim 70 wherein the memory link port comprises an optical port and the memory signals are optical signals, and further wherein the memory hub includes at least one optical transmitter operable to send memory signals and at least one optical receiver operable to receive memory signals, the memory hub being further operable to translate between the optical memory signals and the electrical command, address or data signals.

80. The module of claim 70 wherein the memory module comprises a DIMM.

81. The module of claim 70 wherein the plurality of memory devices comprise DRAM devices.

82. The module of claim 70 wherein each of the memory devices is electrically coupled to the memory hub by a control bus, an address bus and a data bus.

83. The module of claim 70 wherein the memory hub applies command, address or data signals to each of the memory devices simultaneously.

84. The module of claim 70 wherein the memory hub detects address information in a memory signal and applies command, address and data signals to a corresponding memory device.

85. The module of claim 70 wherein the memory hub is positioned at a center of the substrate.

86. A computer system, comprising:

a processor;

a controller electrically coupled to the processor, the controller being operable to receive and transmit memory signals on a memory link; and

a memory module comprising;

a substrate;

a memory hub on the substrate operable to receive memory signals from a memory link port and apply memory signals to the memory link port, the memory signals comprising at least one of command, address or data signals, the memory hub being further operable to translate between memory signals and at least one of electrical command, address or data signals;

a plurality of memory devices on the substrate, the memory devices electrically coupled to the memory hub to receive at least one of command, address, or data signals from the memory hub and to provide data signals to the memory hub;

a first bus coupling a first one of the memory devices to the memory hub;

a second bus coupling a second one of the memory devices to the memory hub;

the first and second buses having substantially a same length, the length being substantially equal to a shortest distance between the memory hub and the first one of the memory devices.

87. The computer system of claim 86 wherein each of the plurality of memory devices are located substantially equidistant from the memory hub.

88. The computer system of claim 86 wherein the memory hub is located at an interior of the circuit board.

89. The computer system of claim 88 wherein the plurality of memory devices are located at a periphery of the circuit board.

90. The computer system of claim 86 wherein the plurality of memory devices comprise more than two memory devices.

91. The computer system of claim 86 wherein the plurality of memory devices comprise more than four memory devices.

92. The computer system of claim 86 wherein the memory link port comprises at least one unidirectional high speed port operable to transmit at least one of command, address and write data signals.

93. The computer system of claim 86 wherein the memory link port comprises at least one unidirectional high speed port operable to transmit at least one of command and read data signals.

94. The computer system of claim 86, wherein the substrate comprises a circuit board.

95. The computer system of claim 86 wherein the memory link port comprises an optical port and the memory signals are optical signals, and further wherein the memory hub includes at least one optical transmitter operable to send memory signals and at least one optical receiver operable to receive memory signals, the memory hub being further operable to translate between the optical memory signals and the electrical command, address or data signals.

96. The computer system of claim 86 wherein the memory module comprises a DIMM.

97. The computer system of claim 86 wherein the plurality of memory devices comprise DRAM devices.

98. The computer system of claim 86 wherein each of the memory devices is electrically coupled to the memory hub by a control bus, an address bus and a data bus.

99. The computer system of claim 86 wherein the memory hub applies command, address or data signals to each of the memory devices simultaneously.

100. The computer system of claim 86 wherein the memory hub detects address information in a memory signal and applies command, address and data signals to a corresponding memory device.

101. The computer system of claim 86 wherein the memory hub is positioned at a center of the substrate.