Microcomputer

• US 20060206746A1
• Filed: 02/21/2006
• Published: 09/14/2006
• Est. Priority Date: 03/08/2005
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamada, Kenji, Ishihara, Hideaki
• Granted Patent: US 7,581,128 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A microcomputer includes a CPU, a program memory for storing a subroutine program, peripheral circuits, a clock circuit, and a voltage drop detection circuit. When the voltage drop detection circuit detects the voltage drop at the end of a power line, a frequency of a clock signal provided through the clock circuit to the CPU is divided down and a supply of a clock signal provided to the peripheral circuits is stopped. The CPU executes the subroutine program, thereby resuming the supply of the clock signal provided to the peripheral circuits.

Claims

1. A microcomputer, comprising:

a central processing unit;

a program memory for storing a control program executed by the central processing unit;

a plurality of peripheral circuits for implementing a predetermined function;

a clock control circuit for controlling a clock signal provided to the central processing unit and the peripheral circuits; and

a voltage drop detection circuit for detecting a drop in a voltage of a power supply below a predetermined level, the voltage drop detection circuit being disposed at an end portion of a power line, wherein

the program memory further stores a subroutine program for causing the central processing unit to execute a clock control process,

when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, a frequency of the clock signal provided through the clock control circuit to the central processing unit is divided down and the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively stop or divides down the clock signal provided to the peripheral circuits.

2. The microcomputer according to claim 1, wherein when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, the clock signal provided to the peripheral circuits is selectively stopped or divided down before the central processing unit executes the subroutine program.

5. The microcomputer according to claim 1, wherein:

the clock control circuit includes a divider circuit and a multiplexer circuit for selecting between a first path for outputting the clock signal provided to the central processing unit without frequency division and a second path for outputting the clock signal provided to the central processing unit through the divider circuit; and

when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, the multiplexer circuit switches to the second path.

6. The microcomputer according to claim 1, further comprising:

an interrupt control circuit for outputting an interrupt request to the central processing unit when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, wherein

when the central processing unit enables the interrupt request, the interrupt control circuit outputs a interrupt vector pointing to a starting address of the subroutine program to the central processing unit.

3. A microcomputer, comprising:

a central processing unit;

a program memory for storing a control program executed by the central processing unit;

a plurality of peripheral circuits for implementing a predetermined function;

a clock control circuit for controlling a clock signal provided to the central processing unit and the peripheral circuits; and

a voltage drop detection circuit for detecting a drop in a voltage of a power source below a predetermined level, the voltage drop detection circuit being disposed at an end portion of a power line, wherein

the program memory further stores a subroutine program for causing the central processing unit to execute a clock control process,

when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, a frequency of the clock signal provided through the clock control circuit to the central processing unit is divided down, a supply of the clock signal provided to the peripheral circuits is stopped, and the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively resumes the supply of the clock signal provided to the peripheral circuits.

4. The microcomputer according to claim 3, wherein

the central processing unit, operating in accordance with the subroutine program, selectively divides down a frequency of the clock signal provided to the peripheral circuits while resuming the supply.

13. The microcomputer according to claim 3, wherein:

the clock control circuit includes a divider circuit and a multiplexer circuit for selecting between a first path for outputting the clock signal provided to the central processing unit without frequency division and a second path for outputting the clock signal provided to the central processing unit through the divider circuit; and

when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, the multiplexer circuit switches to the second path.

14. The microcomputer according to claim 3, further comprising an interrupt control circuit for outputting an interrupt request to the central processing unit when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, wherein when the central processing unit enables the interrupt request, the interrupt control circuit outputs a interrupt vector pointing to a starting address of the subroutine program to the central processing unit.

7. A microcomputer, comprising:

a central processing unit;

a program memory for storing a control program executed by the central processing unit;

a plurality of peripheral circuits for implementing a predetermined function;

a clock control circuit for controlling a clock signal provided to the central processing unit and the peripheral circuits; and

a voltage change detection circuit for detecting that a coefficient of a change in a power supply voltage exceeds a predetermined level, wherein

the program memory further stores a subroutine program for causing the central processing unit to execute a clock control process,

when the voltage change detection circuit detects the change in the power supply voltage, a frequency of the clock signal provided through the clock control circuit to the central processing unit is divided down and the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively stops or divides down the clock signal provided to the peripheral circuits.

8. The microcomputer according to claim 7, wherein

when the voltage change detection circuit detects the change in the voltage, the clock signal provided to the peripheral circuits is selectively stopped or divided down before the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively resumes, stops, or divides down the clock signal provided to the peripheral circuits.

9. A microcomputer, comprising:

a central processing unit;

a program memory for storing a control program executed by the central processing unit;

a plurality of peripheral circuits for implementing a predetermined function;

a clock control circuit for controlling a clock signal provided to the central processing unit and the peripheral circuits; and

a temperature detection circuit for detecting that a temperature exceeds a predetermined range, wherein

the program memory further stores a subroutine program for causing the central processing unit to execute a clock control process,

when the temperature detection circuit detects that the temperature exceeds the predetermined range, a frequency of the clock signal provided through the clock control circuit to the central processing unit is divided down and the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively stops or divides down the clock signal provided to the peripheral circuits.

10. The microcomputer according to claim 9, wherein

when the temperature change detection circuit detects that the temperature exceeds the predetermined range, the clock signal provided to the peripheral circuits is selectively stopped or divided down before the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively resumes, stops, or divides down the clock signal provided to the peripheral circuits.

11. A microcomputer, comprising:

a central processing unit;

a program memory for storing a control program executed by the central processing unit;

a plurality of peripheral circuits for implementing a predetermined function;

a clock control circuit for controlling a clock signal provided to the central processing unit and the peripheral circuits; and

a terminal input detection circuit for detecting that an input of an external terminal becomes a predetermined level, wherein

the program memory further stores a subroutine program for causing the central processing unit to execute a clock control process,

when the terminal input detection circuit detects that the input of the terminal becomes the predetermined level, a frequency of the clock signal provided through the clock control circuit to the central processing unit is divided down and the subroutine program is executed by the central processing unit, and

the central processing unit, operating in accordance with the subroutine program, selectively stops or divides down the clock signal provided to the peripheral circuits.

12. The microcomputer according to claim 11, wherein when the terminal input detection circuit detects that the input of the terminal becomes the predetermined level, the clock signal provided to the peripheral circuits is selectively stopped or divided down before the subroutine program is executed by the central processing unit, and the central processing unit, operating in accordance with the subroutine program, selectively resumes, stops, or divides down the clock signal provided to the peripheral circuits.