Automated system for designing and developing field programmable gate arrays

• US 20060206850A1
• Filed: 05/10/2006
• Published: 09/14/2006
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Pixel Velocity Incorporated
• Original Assignee: David L. Mccubbrey
• Inventors: McCubbrey, David L.
• Granted Patent: US 7,587,699 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/456 Parallelism detection
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O. The mapper includes means for evaluating alternative interconnection routes between logic components within the target FPGA, and means for producing an optimized placement and routing of the logic components and interconnections on the target FPGA. The mapper also generates a low level command listing as a source file that serves as an input file for a conventional low-level FPGA programming tool. From that input file, the tool is able to generate a hardware gate-programming bitstream to be directed to the target FPGA, thereby programming the FPGA with the user-defined algorithm.

Claims

1-20. -20. (canceled)

21. A system for programming a field programmable gate array (FPGA) comprising:

means for analyzing a user-defined algorithm specified in a source code of a high level language and designed to process data vectors with one, two, or more dimensions;

means for identifying the vector processing operations of the source code;

means for mapping the vector processing operations onto logic components of an FPGA; and

means for programming the FPGA with the user-defined algorithm based on the mapping of the logic components.

22. The system of claim 21, wherein the means for analyzing the user-defined algorithm includes means for determining the relative timing between the vector processing operations.

23. The system of claim 22, wherein the means for analyzing the user-defined algorithm includes means for providing an operation dataflow graph that indicates the overall flow of vector processing results between vector operations.

24. The system of claim 21, wherein the means for analyzing the user-defined algorithm includes means for identifying the type of operators and the vector input operands of the vector operations.

25. The system of claim 24, wherein the means for analyzing the user-defined algorithm includes means for identifying the orders and dependencies of the vector operations.

26. The system of claim 21, further comprising:

a library of predefined functions, including first group of image processing functions, a second group of arithmetic functions, and third group of Boolean functions.

27. The system of claim 26, further comprising:

means for determining a first rule set that represents constraints associated with the FPGA and with at least some of the predefined functions in the library, wherein the means for analyzing the user-defined algorithm includes means for accessing the first rule set.

28. The system of claim 27, further comprising:

means for determining a second rule set that represents constraints associated with the FPGA and with at least some of the predefined functions in the library, wherein the means for mapping the logic components includes means for accessing the second rule set.

29. The system of claim 21, wherein the means for mapping the vector processing operators onto FPGA logic components includes means for evaluating alternative component placement and interconnection routes between the logic components.

30. The system of claim 29, wherein the means for mapping the vector processing operators onto FPGA logic components includes means for producing an optimized placement and interconnection routing of the logic components on the FPGA, based on the evaluation of alternative placement and interconnection routes.