Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility

• US 20060208250A1
• Filed: 04/25/2006
• Published: 09/21/2006
• Est. Priority Date: 05/05/2004
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Brown, David E., Sun, Sey-Ping
• Application Number:
  US11/410,062
• Publication Number:
  US 20060208250A1
• Time in Patent Office: Days
• US Class Current: 257/19
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.

Claims

1-9. -9. (canceled)

10. A method of manufacturing a semiconductor device, the method comprising:

forming a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si—

Ge);

forming a transistor comprising source/drain regions and a gate electrode, having an upper surface and side surfaces, over the substrate with a gate dielectric layer therebetween; and

forming a stressed dielectric liner over the side surfaces of the gate electrode and over the source/drain regions, wherein the strained Si layer is either globally strained or locally strained in the source/drain regions.

11. The method according to claim 10, comprising:

forming a sidewall spacer on the side surfaces of the gate electrode;

epitaxially growing a relaxed layer of Si on the strained Si layer;

forming source/drain regions in the relaxed Si layer; and

depositing the stressed dielectric liner on the sidewall spacers, on the relaxed source/drain regions and on portions of the strained Si layer between the sidewall spacers and relaxed source/drain regions, wherein the stressed dielectric liner comprises a layer of silicon nitride, silicon carbide or silicon oxynitride at a thickness of about 200 Å

to about 1000 Å

.

12. The method according to claim 10, comprising forming dielectric sidewall spacers on the side surfaces of the gate electrode by:

depositing an oxide liner on the side surfaces of the gate electrode and on a portion of the strained Si layer adjacent the side surfaces of the gate electrode; and

depositing a nitride layer on the oxide liner.

13. The method according to claim 12, comprising:

forming the source/drain regions in the strained Si layer;

forming a first metal silicide layer on the upper surface of the gate electrode and a second metal silicide layer on the source/drain regions;

removing the dielectric sidewall spacers exposing a portion of the strained Si layer adjacent the side surfaces of the gate electrode; and

forming the stressed dielectric liner on the first metal silicide layer, on the side surfaces of the gate electrode and on the adjacent exposed portions of the strained Si layer.

14. The method according to claim 13, wherein the transistor is a P-channel transistor, the method comprising forming the stressed dielectric layer by depositing a dielectric layer by plasma enhanced chemical vapor deposition under conditions such that it exhibits high compressive stress.

15. The method according to claim 13, wherein the transistor is an N-channel transistor, the method comprising forming the stress dielectric liner by plasma enhanced chemical vapor deposition under such conditions that it exhibits high tensile stress.

16. The method according to claim 13, wherein the transistor is an N-channel transistor, the method comprising forming the stress dielectric liner by:

depositing a dielectric layer; and

treating the dielectric layer such that it exhibits high tensile stress.

17. The method according to claim 16, comprising treating the dielectric layer with ultraviolet or electron-beam radiation such that it exhibits high tensile stress.

18. A method of fabricating a semiconductor device, the method comprising:

forming a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si—

Ge);

forming CMOS transistors comprising an NMOS transistor and a PMOS transistor, each transistor comprising source/drain regions and a gate electrode, having an upper surface and side surfaces, over the substrate with a gate dielectric layer therebetween;

forming sidewall spacers on the side surfaces of each gate electrode;

forming metal silicide layers on the upper surface of each gate electrode and on the surface of the source/drain regions of each transistor;

removing the sidewall spacers from the side surfaces of each of the gate electrodes;

depositing a layer of silicon nitride exhibiting high compressive stress over the NMOS and PMOS transistors;

depositing an oxide or oxynitride liner on the silicon nitride layer exhibiting high compressive stress;

selectively removing the oxide or oxynitride liner and silicon nitride layer exhibiting high compressive stress from the NMOS transistor;

depositing a layer of silicon nitride exhibiting high tensile stress on the NMOS transistor; and

on the PMOS transistor; and

depositing an oxide or oxynitride liner on the silicon nitride layer exhibiting high tensile stress on the NMOS transistor and PMOS transistor, and

selectively removing the oxide or oxynitride liner and the silicon nitride layer exhibiting high tensile stress from the PMOS transistor.

19. The method according to claim 18, comprising:

depositing the layer of silicon nitride exhibiting high compressive stress;

depositing the layer of silicon nitride exhibiting high tensile stress by plasma enhanced chemical vapor deposition at a temperature of 400°

C. to about 480°

C.; and

forming layers of nickel silicide as the metal silicide layers.

20. The method according to claim 18, comprising depositing the layer of silicon nitride exhibiting high compressive stress by depositing multiple layers with intervening plasma treatment in ammonia and nitrogen.