Method for filling recessed micro-structures with metallization in the production of a microelectronic device

• US 20060208272A1
• Filed: 05/23/2006
• Published: 09/21/2006
• Est. Priority Date: 02/04/1998
• Status: Abandoned Application

• Current Assignee: Semitool Incorporated (Applied Materials Incorporated)
• Original Assignee: Semitool Incorporated (Applied Materials Incorporated)
• Inventors: Ritzdorf, Thomas L., Graham, Lyndon W.
• Application Number:
  US11/439,720
• Publication Number:
  US 20060208272A1
• Time in Patent Office: Days
• US Class Current: 257/100
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: C25D 5/18 Electroplating using modulated, pulsed or reversing current
• CPC Class Codes: C25D 5/50 by heat-treatment
• CPC Class Codes: C25D 5/605 Surface topography of the layers, e.g. rough, dendritic or nodular layers
• CPC Class Codes: C25D 5/611 Smooth layers
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.

Claims

1. A semiconductor workpiece comprising:

a surface; and

recessed microstructures at the surface, wherein the recessed microstructures are filled with copper metal by depositing copper into recessed micro-structures using an electrochemical process that generated copper grains that are sufficiently small so as to substantially fill the recessed microstructures and subjecting the surface of the semiconductor workpiece with the deposited copper to an elevated temperature annealing process at a temperature below about 100 degrees Celsius for a time period that was sufficient to increase the grain size of the deposited copper.

2. The semiconductor workpiece in claim 1 wherein the copper was deposited using an electroplating process.

3. The semiconductor workpiece in claim 1 wherein an electroplating waveform was used, at least in part, to ensure the sufficiently small copper grain size generation within the recessed microstructures.

4. The semiconductor workpiece in claim 1 wherein an electroplating solution additive wass used, at least in part, to ensure the sufficiently small copper grain size generation within the recessed microstructures.

5. A semiconductor workpiece comprising:

a surface; and

recessed microstructures at the surface, wherein the recessed microstructures are filled with copper metal by depositing copper into the recessed microstructures using an electrochemical process generating copper grains that are sufficiently small so as to substantially fill the recessed microstructures and subjecting the surface of the semiconductor workpiece and the deposited copper to an elevated temperature annealing process at a temperature at or below about 250 degrees Celsius for a time period of no longer than 15 minutes, which time period was sufficient to increase the grain size of the deposited copper.

6. The semiconductor workpiece in claim 5 wherein an electroplating waveform was used, at least in part, to ensure the sufficiently small metal grain size.

7. The semiconductor workpiece in claim 5 wherein an electroplating solution additive was used, at least in part, to ensure the sufficiently small metal grain size.

8. A semiconductor workpiece comprising:

a surface; and

recessed microstructures at the surface, wherein the recessed microstructures are filled with copper metal by depositing copper into the recessed micro-structures using an electrochemical process generating copper grains that are sufficiently small so as to substantially fill the recessed microstructures and subjecting the surface of the semiconductor workpiece with the deposited copper to an elevated temperature annealing process at a temperature selected to be below a predetermined temperature at which the low-K dielectric layer would suffer substantial degradation.

9. A semiconductor workpiece comprising:

a surface;

a feature that is connected with copper metallization;

at least one low-K dielectric layer over the surface of the semiconductor workpiece including the feature;

recessed microstructures in the at least one low-K dielectric layer; and

a metal seed layer in the recessed microstructures that are filled with copper by electrochemically depositing a copper layer onto the surface of the workpiece using a process that generated copper grains that are sufficiently small to substantially fill the recessed microstructures and annealing the electrochemically deposited copper for a predetermined period of time at an elevated temperature selected to be below a predetermined temperature at which the low-K dielectric layer would substantially degrade and removing copper metallization from the surface of the workpiece except from the recessed microstructures, after the annealing of the copper.

10. The semiconductor workpiece of claim 9 further comprising at least one barrier layer over the dielectric layer and under the metal seed layer.

11. The semiconductor workpiece of claim 9 wherein the seed layer comprises a chemical vapor deposited seed layer.

12. The semiconductor workpiece of claim 9 further comprising at least one adhesion layer over the dielectric layer and under the metal seed layer.

15. The semiconductor workpiece of claim 9 further comprising the annealing taking place at a temperature corresponding to a baking temperature of the low-K dielectric.

13. A semiconductor workpiece comprising:

a surface;

a feature that is connected with copper metallization;

at least one low-K dielectric layer over the surface of the semiconductor workpiece including the feature;

recessed microstructures in the at least one low-K dielectric layer; and

a metal seed layer in the recessed microstructures that are filled with copper by electrolytically depositing a copper layer onto the surface of the workpiece using an electrolytic process that generated copper grains that are sufficiently small to substantially fill the recessed microstructures and subjecting the electrolytically deposited copper layer to an annealing process at a temperature at or below about 250 to 300 degrees Celsius to increase the copper grain size.

14. A semiconductor workpiece comprising:

a surface;

a feature that is connected with copper metallization;

at least one low-K dielectric layer over the surface of the semiconductor workpiece including the feature;

recessed microstructures in the at least one low-K dielectric layer;

a metal seed layer in the recessed microstructures that are filled with copper by electrolytically depositing a copper layer to the surface of the workpiece using an electrolytic process that generated copper grains having a size sufficiently small to substantially fill the recessed microstructures and subjecting the electrolytically deposited copper layer to an annealing process at a temperature below which the low-K dielectric layer substantially degrades; and

at least one barrier layer over the low-K dielectric layer and under the metal seed layer.

16. A semiconductor workpiece comprising;

a base having a surface;

a dielectric layer carried on the surface of the base;

recessed sub-micron structures formed in the dielectric layer;

a conductive seed layer on the dielectric layer and in the recessed sub-micron structures wherein the recessed sub-micron structures are filled with copper by contacting the conductive seed layer with a copper-containing electroplating solution, applying electroplating power to the seed layer at a first power level for a predetermined first period of time, then applying electroplating power to the seed layer a higher second power level for a time sufficient to electrolytically substantially fill the recessed sub-micron structures with copper metal and to deposit excess copper metal which extends above a surface of the dielectric layer; and

wherein a resistivity of the electrolytically deposited copper metal the recessed sub-micron structures was reduced by subjecting the workpiece to an elevated temperature annealing process at a temperature that is at or below about 250 degrees Celsius.

17. The semiconductor workpiece of claim 16 wherein the annealing process was carried out at a temperature that is at or below about 100 degrees Celsius.

18. The semiconductor workpiece of claim 16 wherein the annealing process was carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.

19. The semiconductor workpiece of claim 16 further comprising at least one barrier layer over the dielectric layer and under the conductive seed layer.